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/linux-5.10/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-cti1 What: /sys/bus/coresight/devices/<cti-name>/enable
5 Description: (RW) Enable/Disable the CTI hardware.
7 What: /sys/bus/coresight/devices/<cti-name>/powered
11 Description: (Read) Indicate if the CTI hardware is powered.
13 What: /sys/bus/coresight/devices/<cti-name>/ctmid
19 What: /sys/bus/coresight/devices/<cti-name>/nr_trigger_cons
23 Description: (Read) Number of devices connected to triggers on this CTI
25 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/name
31 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_signals
37 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_types
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/linux-5.10/Documentation/devicetree/bindings/arm/
Dcoresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
12 to one or more CoreSight components and/or a CPU, with CTIs interconnected in
15 not part of the CoreSight graph described in the general CoreSight bindings
16 file coresight.txt.
18 The CTI component properties define the connections between the individual
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Dcoresight.txt1 * CoreSight Components:
3 CoreSight components are compliant with the ARM CoreSight architecture
8 sink. Each CoreSight component device should use these properties to describe
11 * Required properties for all components *except* non-configurable replicators
12 and non-configurable funnels:
16 - Embedded Trace Buffer (version 1.0):
17 "arm,coresight-etb10", "arm,primecell";
19 - Trace Port Interface Unit:
20 "arm,coresight-tpiu", "arm,primecell";
22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
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/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhi6220-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * dtsi file for Hisilicon Hi6220 coresight
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
17 clock-names = "apb_pclk";
19 out-ports {
22 remote-endpoint =
28 in-ports {
31 remote-endpoint =
39 compatible = "arm,coresight-tmc", "arm,primecell";
42 clock-names = "apb_pclk";
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/linux-5.10/drivers/hwtracing/coresight/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for CoreSight drivers.
5 obj-$(CONFIG_CORESIGHT) += coresight.o
6 coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
7 coresight-sysfs.o
8 obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
9 coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
10 coresight-tmc-etr.o
11 obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o
12 obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Coresight configuration
5 menuconfig CORESIGHT config
6 tristate "CoreSight Tracing Support"
12 This framework provides a kernel interface for the CoreSight debug
14 a topological view of the CoreSight components based on a DT
19 module will be called coresight.
21 if CORESIGHT
23 tristate "CoreSight Link and Sink drivers"
25 This enables support for CoreSight link and sink drivers that are
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Dcoresight-cti.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/coresight.h>
18 #include "coresight-priv.h"
22 * 0x000 - 0x144: CTI programming and status
23 * 0xEDC - 0xEF8: CTI integration test.
24 * 0xF00 - 0xFFC: Coresight management registers.
26 /* CTI programming registers */
41 #define ITCHINACK 0xEDC /* WO CTI CSSoc 400 only*/
42 #define ITTRIGINACK 0xEE0 /* WO CTI CSSoc 400 only*/
43 #define ITCHOUT 0xEE4 /* WO RW-600 */
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Dcoresight-cti-platform.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/coresight.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
14 #include "coresight-cti.h"
15 #include "coresight-priv.h"
17 /* Number of CTI signals in the v8 architecturally defined connection */
22 /* CTI device tree trigger connection node keyword */
23 #define CTI_DT_CONNS "trig-conns"
25 /* CTI device tree connection property keywords */
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
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Dcoresight-cti-core.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/coresight.h>
22 #include "coresight-priv.h"
23 #include "coresight-cti.h"
26 * CTI devices can be associated with a PE, or be connected to CoreSight
30 * We assume that the non-CPU CTIs are always powered as we do with sinks etc.
36 /* net of CTI devices connected via CTM */
43 dev_get_drvdata(csdev->dev.parent)
52 * CTI naming. CTI bound to cores will have the name cti_cpu<N> where
56 * CTI device name list - for CTI not bound to cores.
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Dcoresight-cti-sysfs.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/coresight.h>
15 #include "coresight-cti.h"
25 * include\dt-bindings\arm\coresight-cti-dt.h
85 struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); in enable_show()
87 enable_req = atomic_read(&drvdata->config.enable_req_count); in enable_show()
88 spin_lock(&drvdata->spinlock); in enable_show()
89 powered = drvdata->config.hw_powered; in enable_show()
90 enabled = drvdata->config.hw_enabled; in enable_show()
91 spin_unlock(&drvdata->spinlock); in enable_show()
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Dcoresight-core.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/coresight.h>
22 #include "coresight-etm-perf.h"
23 #include "coresight-priv.h"
28 * struct coresight_node - elements of a path, from source to sink
38 * When operating Coresight drivers from the sysFS interface, only a single
85 if (i_csdev == csdev || !i_csdev->enable || in coresight_id_match()
86 i_csdev->type != CORESIGHT_DEV_TYPE_SOURCE) in coresight_id_match()
90 trace_id = source_ops(csdev)->trace_id(csdev); in coresight_id_match()
91 i_trace_id = source_ops(i_csdev)->trace_id(i_csdev); in coresight_id_match()
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/linux-5.10/Documentation/trace/coresight/
Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
4 CoreSight Embedded Cross Trigger (CTI & CTM).
11 --------------------
13 The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
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Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
9 ------------
11 Coresight is an umbrella of technologies allowing for the debugging of ARM
24 flows through the coresight system (via ATB bus) using links that are connecting
25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight
28 host without fear of filling up the onboard coresight memory buffer.
30 At typical coresight system would look like this::
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
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/linux-5.10/arch/arm/include/asm/
Dcti.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/hardware/coresight.h>
35 * CoreSight v1.0 Architecture Specification
41 * struct cti - cross trigger interface struct
42 * @base: mapped virtual address for the cti base
43 * @irq: irq number for the cti
47 * cti struct used to operate cti registers.
49 struct cti { struct
56 * cti_init - initialize the cti instance argument
57 * @cti: cti instance
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/linux-5.10/arch/arm64/boot/dts/qcom/
Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&intc>;
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/linux-5.10/include/dt-bindings/arm/
Dcoresight-cti-dt.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * types on CoreSight CTI.
/linux-5.10/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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