Lines Matching +full:coresight +full:- +full:cti
2 Coresight - HW Assisted Tracing on ARM
9 ------------
11 Coresight is an umbrella of technologies allowing for the debugging of ARM
24 flows through the coresight system (via ATB bus) using links that are connecting
25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight
28 host without fear of filling up the onboard coresight memory buffer.
30 At typical coresight system would look like this::
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
43 | |->### | ! | |->### | ! | ! . | || DAP ||
49 *****************************************************************<-|
63 | * ===== F =====<---------|
65 |-->:: CTI ::<!! === N ===
69 |------>&& ETB &&<......II I =======
75 |------>& TPIU &<......II I DAP = Debug Access Port
78 ; CTI = Cross Trigger Interface
84 all trace data are carried out-of-band on the ATB bus. The CTM provides
85 a way to aggregate and distribute signals between CoreSight components.
87 The coresight framework provides a central point to represent, configure and
88 manage coresight devices on a platform. This first implementation centers on
91 intricate IP blocks such as STM and CTI.
95 ---------------------------
111 TMC-ETR:
113 TMC-ETF:
115 CTI:
123 Funnel, replicator (intelligent or not), TMC-ETR
125 ETBv1.0, ETB1.1, TPIU, TMC-ETF
127 CTI
131 --------------------
133 See Documentation/devicetree/bindings/arm/coresight.txt for details.
140 ----------------------------
142 The coresight framework provides a central point to represent, configure and
143 manage coresight devices on a platform. Any coresight compliant device can
154 show up under /sys/bus/coresight/devices, as showns here for a TC2 platform::
156 root:~# ls /sys/bus/coresight/devices/
190 drvdata->dev = &adev->dev;
201 --------------------
203 The devices that appear on the "coresight" bus were named the same as their
209 root:~# ls /sys/bus/coresight/devices/
216 devices are a bit cryptic and non-obvious. Thus, a new naming scheme was
227 <device_type_prefix> - A prefix specific to the type of the device
228 N - a sequential number assigned based on the order
235 root:~# ls /sys/bus/coresight/devices/
245 -----------------------
247 Each CoreSight component has a ``connections`` directory which will contain
248 links to other CoreSight components. This allows the user to explore the trace
251 which CTI devices are connected to a given component. This directory contains a
257 linaro-developer:~# ls - l /sys/bus/coresight/devices/etm0/connections
258 <file details> cti_cpu0 -> ../../../23020000.cti/cti_cpu0
260 <file details> out:0 -> ../../../230c0000.funnel/funnel2
264 linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel2/connections
265 <file details> in:0 -> ../../../23040000.etm/etm0
266 <file details> in:1 -> ../../../23140000.etm/etm3
267 <file details> in:2 -> ../../../23240000.etm/etm4
268 <file details> in:3 -> ../../../23340000.etm/etm5
270 <file details> out:0 -> ../../../20040000.funnel/funnel0
274 linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel0/connections
275 <file details> in:0 -> ../../../220c0000.funnel/funnel1
276 <file details> in:1 -> ../../../230c0000.funnel/funnel2
278 <file details> out:0 -> ../../../20010000.etf/tmc_etf0
283 linaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etf0/connections
284 <file details> cti_sys0 -> ../../../20020000.cti/cti_sys0
285 <file details> in:0 -> ../../../20040000.funnel/funnel0
287 <file details> out:0 -> ../../../20150000.funnel/funnel4
291 linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel4/connections
292 <file details> in:0 -> ../../../20010000.etf/tmc_etf0
293 <file details> in:1 -> ../../../20140000.etf/tmc_etf1
295 <file details> out:0 -> ../../../20120000.replicator/replicator0
299 linaro-developer:~# ls -l /sys/bus/coresight/devices/replicator0/connections
300 <file details> in:0 -> ../../../20150000.funnel/funnel4
302 <file details> out:0 -> ../../../20030000.tpiu/tpiu0
303 <file details> out:1 -> ../../../20070000.etr/tmc_etr0
307 linaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etr0/connections
308 <file details> cti_sys0 -> ../../../20020000.cti/cti_sys0
309 <file details> in:0 -> ../../../20120000.replicator/replicator0
318 via the CTM. See (:doc:`coresight-ect`) [#fourth]_ for further details.
321 linaro-developer:~# ls -l /sys/bus/coresight/devices/cti_sys0/connections
323 <file details> stm0 -> ../../../20100000.stm/stm0
324 <file details> tmc_etf0 -> ../../../20010000.etf/tmc_etf0
325 <file details> tmc_etr0 -> ../../../20070000.etr/tmc_etr0
326 <file details> tpiu0 -> ../../../20030000.tpiu/tpiu0
330 -----------------------------
332 There are two ways to use the Coresight framework:
335 2. interacting directly with the Coresight devices using the sysFS interface.
338 requires a deep understanding of the Coresight HW. The following sections
343 Before trace collection can start, a coresight sink needs to be identified.
348 root:/sys/bus/coresight/devices# ls
351 root:/sys/bus/coresight/devices# ls 20010000.etb
353 root:/sys/bus/coresight/devices# echo 1 > 20010000.etb/enable_sink
354 root:/sys/bus/coresight/devices# cat 20010000.etb/enable_sink
356 root:/sys/bus/coresight/devices#
363 root:/sys/bus/coresight/devices# echo 1 > 2201c000.ptm/enable_source
364 root:/sys/bus/coresight/devices# cat 2201c000.ptm/enable_source
366 root:/sys/bus/coresight/devices# cat 20010000.etb/status
370 RAM wrt ptr: 0x19d3 <----- The write pointer is moving
375 root:/sys/bus/coresight/devices#
379 root:/sys/bus/coresight/devices# echo 0 > 2201c000.ptm/enable_source
380 root:/sys/bus/coresight/devices#
384 root:/sys/bus/coresight/devices# dd if=/dev/20010000.etb \
389 root:/sys/bus/coresight/devices#
391 The file cstrace.bin can be decompressed using "ptm2human", DS-5 or Trace32.
393 Following is a DS-5 output of an experimental loop that increments a variable up
395 wealth of possibilities that coresight provides.
407 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
413 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
418 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
423 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
428 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
433 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
450 Coresight tracers are represented using the Perf framework's Performance
453 scheduled. When configured in a system, Coresight PMUs will be listed when
456 linaro@linaro-nano:~$ ./perf list pmu
458 List of pre-defined events (to be used in -e):
462 linaro@linaro-nano:~$
467 A Coresight PMU works the same way as any other PMU, i.e the name of the PMU is
469 Coresight system will typically have more than one sink, the name of the sink to
477 On older kernels, this may need to be found from the list of coresight devices,
478 available under ($SYSFS)/bus/coresight/devices/::
480 root:~# ls /sys/bus/coresight/devices/
483 root@linaro-nano:~# perf record -e cs_etm/@tmc_etr0/u --per-thread program
493 More information on the above and other example on how to use Coresight with
504 perf record -e cs_etm/@tmc_etr0/u --per-thread
509 The --itrace option controls the type and frequency of synthesized events
512 Note that only 64-bit programs are currently supported - further work is
513 required to support instruction decode of 32-bit Arm programs.
517 ---------------------------------------------------------------------
519 'perf inject' accepts the --itrace option in which case tracing data is
523 perf inject --itrace --strip -i perf.data -o perf.data.new
530 $ gcc-5 -O3 sort.c -o sort
531 $ taskset -c 2 ./sort
535 $ perf record -e cs_etm/@tmc_etr0/u --per-thread taskset -c 2 ./sort
541 $ perf inject -i perf.data -o inj.data --itrace=il64 --strip
542 $ create_gcov --binary=./sort --profile=inj.data --gcov=sort.gcov -gcov_version=1
543 $ gcc-5 -O3 -fauto-profile=sort.gcov sort.c -o sort_autofdo
544 $ taskset -c 2 ./sort_autofdo
550 -------------------------
552 Using the System Trace Macrocell module is the same as the tracers - the only
556 As with any other CoreSight component, specifics about the STM tracer can be
559 root@genericarmv8:~# ls /sys/bus/coresight/devices/stm0
567 root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
568 root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/stm0/enable_source
573 root@genericarmv8:~# ls -l /dev/stm0
574 crw------- 1 root root 10, 61 Jan 3 18:11 /dev/stm0
577 Details on how to use the generic STM API can be found here:- :doc:`../stm` [#second]_.
579 The CTI & CTM Modules
580 ---------------------
582 The CTI (Cross Trigger Interface) provides a set of trigger signals between
587 (:doc:`coresight-ect`) [#fourth]_.
590 .. [#first] Documentation/ABI/testing/sysfs-bus-coresight-devices-stm
594 .. [#third] https://github.com/Linaro/perf-opencsd
596 .. [#fourth] Documentation/trace/coresight/coresight-ect.rst