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/qemu/scripts/kvm/
H A Dvmxcap76 # All 64 bits in the tertiary controls MSR are allowed-1
108 controls = [ variable
125 name = 'pin-based controls',
138 name = 'primary processor-based controls',
149 17: 'Activate tertiary controls',
168 name = 'secondary processor-based controls',
202 name = 'tertiary processor-based controls',
210 name = 'VM-Exit controls',
212 2: 'Save debug controls',
224 31: 'Activate secondary VM-exit controls',
[all …]
/qemu/include/hw/s390x/
H A Ds390-pci-inst.h46 /* Modify PCI Function Controls */
56 /* Store PCI Function Controls status codes */
64 /* FIB function controls */
70 /* FIB function controls */
80 uint8_t fc; /* function controls */
H A Ds390-pci-clp.h182 uint8_t oc; /* operation controls */
/qemu/hw/char/
H A Dparallel.c171 /* Controls not correct for EPP address cycle, so do nothing */ in parallel_ioport_write_hw()
186 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_write_hw()
213 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_write_hw2()
238 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_write_hw4()
326 /* Controls not correct for EPP addr cycle, so do nothing */ in parallel_ioport_read_hw()
342 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_read_hw()
371 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_read_hw2()
399 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_read_hw4()
/qemu/hw/virtio/
H A Dvhost-user-snd.c21 .end = endof(struct virtio_snd_config, controls)},
38 DEFINE_PROP_BIT64("controls", VHostUserBase,
/qemu/docs/
H A Dnvdimm.txt39 "share=on/off" controls the visibility of guest writes. If
46 "readonly=on/off" controls whether the file $PATH is opened read-only or
53 "unarmed" controls the ACPI NFIT NVDIMM Region Mapping Structure "NVDIMM
/qemu/docs/system/i386/
H A Dtdx.rst44 - PKS (bit 30) controls whether Supervisor Protection Keys is exposed to TD,
46 - PERFMON (bit 63) controls whether PMU is exposed to TD.
/qemu/linux-user/hppa/
H A Dtarget_signal.h53 * sigaltstack controls
/qemu/include/hw/ssi/
H A Dnpcm_pspi.h36 * Each PSPI has a shared bank of registers, and controls up to four chip
H A Dnpcm7xx_fiu.h51 * Each FIU has a shared bank of registers, and controls up to four chip
/qemu/linux-user/sparc/
H A Dtarget_signal.h52 * sigaltstack controls
/qemu/linux-user/generic/
H A Dsignal.h65 * sigaltstack controls
/qemu/include/standard-headers/linux/
H A Dvirtio_snd.h29 uint32_t controls; member
362 /* 0 ... virtio_snd_config::controls - 1 */
482 /* 0 ... virtio_snd_config::controls - 1 */
H A Dinput.h315 * @interval: controls how soon the effect can be re-triggered
367 * @right_coeff: controls how fast the force grows when the joystick moves
H A Dinput-event-codes.h337 #define KEY_RFKILL 247 /* Key that controls all radios */
512 #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */
563 #define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */
/qemu/hw/misc/
H A Dmps2-scc.c246 * On some boards bit 0 controls board-specific remapping; in mps2_scc_write()
251 * TODO: on the AN536 this register controls reset and halt in mps2_scc_write()
265 * TODO: for AN536 this controls whether flash and ATCM are in mps2_scc_write()
/qemu/include/hw/misc/
H A Dmps2-scc.h25 * bit 0. Boards where this bit controls memory remapping should
/qemu/linux-user/alpha/
H A Dtarget_signal.h51 * sigaltstack controls
/qemu/linux-user/mips64/
H A Dtarget_signal.h54 * sigaltstack controls
/qemu/linux-user/mips/
H A Dtarget_signal.h55 * sigaltstack controls
/qemu/docs/interop/
H A Ddbus.rst63 unless additional controls such as SELinux or AppArmor are
/qemu/migration/
H A Dcpu-throttle.c35 /* vcpu throttling controls */
/qemu/semihosting/
H A Dconfig.c7 * This controls the configuration of semihosting for all guest
/qemu/scripts/performance/
H A DtopN_perf.py74 which controls use of the performance events system by
/qemu/contrib/plugins/
H A Dips.c5 * particular number of Instructions Per Second (IPS). This controls

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