/qemu/scripts/kvm/ |
H A D | vmxcap | 76 # All 64 bits in the tertiary controls MSR are allowed-1 108 controls = [ variable 125 name = 'pin-based controls', 138 name = 'primary processor-based controls', 149 17: 'Activate tertiary controls', 168 name = 'secondary processor-based controls', 202 name = 'tertiary processor-based controls', 210 name = 'VM-Exit controls', 212 2: 'Save debug controls', 224 31: 'Activate secondary VM-exit controls', [all …]
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/qemu/include/hw/s390x/ |
H A D | s390-pci-inst.h | 46 /* Modify PCI Function Controls */ 56 /* Store PCI Function Controls status codes */ 64 /* FIB function controls */ 70 /* FIB function controls */ 80 uint8_t fc; /* function controls */
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H A D | s390-pci-clp.h | 182 uint8_t oc; /* operation controls */
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/qemu/hw/char/ |
H A D | parallel.c | 171 /* Controls not correct for EPP address cycle, so do nothing */ in parallel_ioport_write_hw() 186 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_write_hw() 213 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_write_hw2() 238 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_write_hw4() 326 /* Controls not correct for EPP addr cycle, so do nothing */ in parallel_ioport_read_hw() 342 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_read_hw() 371 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_read_hw2() 399 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_read_hw4()
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/qemu/hw/virtio/ |
H A D | vhost-user-snd.c | 21 .end = endof(struct virtio_snd_config, controls)}, 38 DEFINE_PROP_BIT64("controls", VHostUserBase,
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/qemu/docs/ |
H A D | nvdimm.txt | 39 "share=on/off" controls the visibility of guest writes. If 46 "readonly=on/off" controls whether the file $PATH is opened read-only or 53 "unarmed" controls the ACPI NFIT NVDIMM Region Mapping Structure "NVDIMM
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/qemu/docs/system/i386/ |
H A D | tdx.rst | 44 - PKS (bit 30) controls whether Supervisor Protection Keys is exposed to TD, 46 - PERFMON (bit 63) controls whether PMU is exposed to TD.
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/qemu/linux-user/hppa/ |
H A D | target_signal.h | 53 * sigaltstack controls
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/qemu/include/hw/ssi/ |
H A D | npcm_pspi.h | 36 * Each PSPI has a shared bank of registers, and controls up to four chip
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H A D | npcm7xx_fiu.h | 51 * Each FIU has a shared bank of registers, and controls up to four chip
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/qemu/linux-user/sparc/ |
H A D | target_signal.h | 52 * sigaltstack controls
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/qemu/linux-user/generic/ |
H A D | signal.h | 65 * sigaltstack controls
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/qemu/include/standard-headers/linux/ |
H A D | virtio_snd.h | 29 uint32_t controls; member 362 /* 0 ... virtio_snd_config::controls - 1 */ 482 /* 0 ... virtio_snd_config::controls - 1 */
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H A D | input.h | 315 * @interval: controls how soon the effect can be re-triggered 367 * @right_coeff: controls how fast the force grows when the joystick moves
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H A D | input-event-codes.h | 337 #define KEY_RFKILL 247 /* Key that controls all radios */ 512 #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ 563 #define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */
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/qemu/hw/misc/ |
H A D | mps2-scc.c | 246 * On some boards bit 0 controls board-specific remapping; in mps2_scc_write() 251 * TODO: on the AN536 this register controls reset and halt in mps2_scc_write() 265 * TODO: for AN536 this controls whether flash and ATCM are in mps2_scc_write()
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/qemu/include/hw/misc/ |
H A D | mps2-scc.h | 25 * bit 0. Boards where this bit controls memory remapping should
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/qemu/linux-user/alpha/ |
H A D | target_signal.h | 51 * sigaltstack controls
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/qemu/linux-user/mips64/ |
H A D | target_signal.h | 54 * sigaltstack controls
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/qemu/linux-user/mips/ |
H A D | target_signal.h | 55 * sigaltstack controls
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/qemu/docs/interop/ |
H A D | dbus.rst | 63 unless additional controls such as SELinux or AppArmor are
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/qemu/migration/ |
H A D | cpu-throttle.c | 35 /* vcpu throttling controls */
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/qemu/semihosting/ |
H A D | config.c | 7 * This controls the configuration of semihosting for all guest
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/qemu/scripts/performance/ |
H A D | topN_perf.py | 74 which controls use of the performance events system by
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/qemu/contrib/plugins/ |
H A D | ips.c | 5 * particular number of Instructions Per Second (IPS). This controls
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