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/qemu/docs/system/arm/
H A Dimx8mp-evk.rst15 * 3 USDHC Storage Controllers
18 * 2 Designware USB 3 Controllers
19 * 5 GPIO Controllers
20 * 6 I2C Controllers
21 * 3 SPI Controllers
H A Dsabrelite.rst22 * 3 I2C controllers
23 * 7 GPIO controllers
24 * 4 SDHC storage controllers
25 * 4 USB 2.0 host controllers
26 * 5 ECSPI controllers
H A Dimx25-pdk.rst17 - GPIO controllers
19 - USB controllers
H A Dnuvoton.rst5 designed to be used as Baseboard Management Controllers (BMCs) in various
48 * OTP controllers (no protection features)
H A Dkzm.rst17 - GPIO controllers
H A Dhighbank.rst19 - XGMAC ethernet controllers
H A Daspeed.rst55 * SD/MMC storage controllers
60 * Ethernet controllers
272 * SD/MMC storage controllers
277 * Ethernet controllers
/qemu/docs/system/devices/
H A Dnvme.rst124 This will create an NVM subsystem with two controllers. Having controllers
128 Specifies that the namespace will be attached to all controllers in the
131 are always automatically attached to all controllers (also when controllers
136 not attached to any controllers initially. A shared namespace with this set
137 to ``on`` will never be automatically attached to controllers.
149 controllers. NSID 3 will be a private namespace due to ``shared=off`` and only
152 controllers.
312 by the NVMe device. Virtual function controllers will not report SR-IOV.
316 the secondary controllers. Implicitly sets the number of primary
321 all the secondary controllers. Implicitly sets the number of primary
H A Dusb.rst9 USB controllers
33 standalone or with companion controllers (UHCI, OHCI) for USB 1.1
39 controllers for USB 1.1 devices too. Each controller creates its own
74 The UHCI and OHCI controllers can attach to a USB bus created by EHCI
75 as companion controllers. This is done by specifying the ``masterbus``
79 controller with six ports has three UHCI companion controllers with
H A Digb.rst7 igb is a family of Intel's gigabit ethernet controllers. In QEMU, 82576
/qemu/docs/specs/
H A Driscv-aia.rst20 When running TCG, all controllers are emulated in userspace, including machine mode
30 machine will use the provided in-kernel APLIC and IMSIC controllers. If the user
/qemu/docs/system/ppc/
H A Dpowernv.rst34 * I2C controllers (yet to be merged).
35 * NPU/NPU2/NPU3 controllers.
36 * EEH support for PCIe Host bridge controllers.
109 Here is a full example with two different storage controllers on
/qemu/hw/pci/
H A DKconfig15 # selected by interrupt controllers that do not support MSI,
H A Dmsi.c42 * Flag for interrupt controllers to declare broken MSI/MSI-X support.
47 * It is preferable for controllers to set this to true (non-broken) even if
49 * type and do not attempt to enable MSI/MSI-X with interrupt controllers not
53 * TODO: some existing controllers violate the above rule. Identify and fix them.
/qemu/docs/config/
H A Dq35-emulated.cfg23 # controllers; the user will then have to explicitly add
167 # EHCI controller + UHCI companion controllers.
203 # EHCI controller + UHCI companion controllers.
H A Dich9-ehci-uhci.cfg7 # controllers as multifunction device in PCI slot "1d".
H A Dq35-virtio-graphical.cfg23 # controllers; the user will then have to explicitly add
216 # reduce the number of PCI Express controllers in the
/qemu/docs/devel/
H A Dreset.rst74 be several reset sources/controllers of a given object. The interface handles
75 everything and the different reset controllers do not need to know anything
77 controllers end their reset operation. This point is handled internally by
143 the object does not need to care how many of reset controllers it has and how
H A Dmemory.rst5 The memory API models the memory and I/O buses and controllers of a QEMU
10 - memory controllers that can dynamically reroute physical memory regions
21 buses, memory controllers, and memory regions that have been rerouted.
/qemu/include/hw/sd/
H A Dsd.h203 * bcm2835 which have two SD controllers and connect a single SD card
208 /* Functions to be used by SD devices to report back to qdevified controllers */
/qemu/docs/system/
H A Dtarget-sparc.rst45 - Slave I/O: timers, interrupt controllers, Zilog serial ports,
H A Dtarget-mips.rst45 - PC-style IRQ and DMA controllers
/qemu/hw/isa/
H A Disa-superio.c43 warn_report("superio: ignoring %td parallel controllers", in isa_superio_realize()
82 warn_report("superio: ignoring %td serial controllers", in isa_superio_realize()
/qemu/docs/
H A Dglossary.rst42 UARTs, PCI controllers, PCI cards, VGA controllers, and many more.
/qemu/tests/qtest/
H A Dsdhci-test.c2 * QTest testcase for SDHCI controllers

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