| /linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | fixed-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Binding for simple fixed-rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
15 const: fixed-clock
17 "#clock-cells":
20 clock-frequency: true
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| /linux-5.10/drivers/clk/ |
| D | clk-fixed-rate.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * Fixed rate clock implementation
9 #include <linux/clk-provider.h>
18 * DOC: basic fixed-rate clock that cannot gate
20 * Traits of this clock:
21 * prepare - clk_(un)prepare only ensures parents are prepared
22 * enable - clk_enable only ensures parents are enabled
23 * rate - rate is always a fixed value. No clk_set_rate support
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| D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
80 unsigned long accuracy; member
113 if (!core->rpm_enabled) in clk_pm_runtime_get()
116 ret = pm_runtime_get_sync(core->dev); in clk_pm_runtime_get()
118 pm_runtime_put_noidle(core->dev); in clk_pm_runtime_get()
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| /linux-5.10/Documentation/timers/ |
| D | timekeeping.rst | 2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
22 Clock sources
23 -------------
25 The purpose of the clock source is to provide a timeline for the system that
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| /linux-5.10/Documentation/hwmon/ |
| D | pc87360.rst | 22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
60 PC87366 11 3 3 3-4 0xE9
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| D | shtc1.rst | 41 -----------
48 address 0x70. See Documentation/i2c/instantiating-devices.rst for methods to
53 1. blocking (pull the I2C clock line down while performing the measurement) or
54 non-blocking mode. Blocking mode will guarantee the fastest result but
55 the I2C bus will be busy during that time. By default, non-blocking mode
56 is used. Make sure clock-stretching works properly on your device if you
58 2. high or low accuracy. High accuracy is used by default and using it is
61 sysfs-Interface
62 ---------------
65 - temperature input
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| D | sht3x.rst | 6 * Sensirion SHT3x-DIS
16 - David Frey <david.frey@sensirion.com>
17 - Pascal Sachs <pascal.sachs@sensirion.com>
20 -----------
22 This driver implements support for the Sensirion SHT3x-DIS chip, a humidity
29 Documentation/i2c/instantiating-devices.rst for methods to instantiate the device.
33 1. blocking (pull the I2C clock line down while performing the measurement) or
34 non-blocking mode. Blocking mode will guarantee the fastest result but
35 the I2C bus will be busy during that time. By default, non-blocking mode
36 is used. Make sure clock-stretching works properly on your device if you
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| D | lm63.rst | 45 -----------
53 - No low limit for local temperature.
54 - No critical limit for local temperature.
55 - Critical limit for remote temperature can be changed only once. We
56 will consider that the critical limit is read-only.
67 store the value in an 8-bit register and have a selectable clock divider
68 to make sure that the result will fit in the register, the LM63 uses 16-bit
93 The LM96163 is an enhanced version of LM63 with improved temperature accuracy
|
| /linux-5.10/include/linux/ |
| D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
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| /linux-5.10/arch/arm/boot/dts/ |
| D | alphascale-asm9260.dtsi | 2 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
7 #include <dt-bindings/clock/alphascale,asm9260.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&icoll>;
20 #address-cells = <0>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
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| D | pxa300-raumfeld-tuneable-clock.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/maxim,max9485.h>
6 xo_27mhz: oscillator-27mhz {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <27000000>;
10 clock-accuracy = <100>;
14 compatible = "simple-audio-card";
15 simple-audio-card,name = "Raumfeld Speaker";
16 #address-cells = <1>;
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| D | pxa300-raumfeld-speaker-one.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
9 compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300";
13 #sound-dai-cells = <0>;
14 Vdd-supply = <®_3v3>;
15 Vdda-supply = <®_va_5v0>;
18 xo_11mhz: oscillator-11mhz {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
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| D | sun8i-v3s.dtsi | 4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
45 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
51 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
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| /linux-5.10/Documentation/sound/designs/ |
| D | timestamping.rst | 7 - Trigger_tstamp is the system time snapshot taken when the .trigger
11 estimate with a delay. In the latter two cases, the low-level driver
17 - tstamp is the current system timestamp updated during the last
19 The difference (tstamp - trigger_tstamp) defines the elapsed time.
29 - ``avail`` reports how much can be written in the ring buffer
30 - ``delay`` reports the time it will take to hear a new sample after all
43 ascii-art, this could be represented as follows (for the playback
47 --------------------------------------------------------------> time
53 |< codec delay >|<--hw delay-->|<queued samples>|<---avail->|
54 |<----------------- delay---------------------->| |
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| /linux-5.10/drivers/clk/at91/ |
| D | dt-compat.c | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
31 const char *name = np->name; in of_sama5d2_clk_audio_pll_frac_setup()
48 "atmel,sama5d2-clk-audio-pll-frac",
54 const char *name = np->name; in of_sama5d2_clk_audio_pll_pad_setup()
71 "atmel,sama5d2-clk-audio-pll-pad",
77 const char *name = np->name; in of_sama5d2_clk_audio_pll_pmc_setup()
94 "atmel,sama5d2-clk-audio-pll-pmc",
148 if (of_property_read_string(np, "clock-output-names", &name)) in of_sama5d2_clk_generated_setup()
149 name = gcknp->name; in of_sama5d2_clk_generated_setup()
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| /linux-5.10/arch/x86/kernel/ |
| D | tsc_msr.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include <asm/intel-family.h>
23 * lot of accuracy which leads to clock drift. As far as we know Bay Trail SoCs
26 * unclear if the root PLL outputs are used directly by the CPU clock PLL or
30 * So we can create a simplified model of the CPU clock setup using a reference
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
62 * Penwell and Clovertrail use spread spectrum clock,
161 * MSR-based CPU/TSC frequency discovery for certain CPUs.
179 freq_desc = (struct freq_desc *)id->driver_data; in cpu_khz_from_msr()
180 if (freq_desc->use_msr_plat) { in cpu_khz_from_msr()
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| D | pvclock.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* paravirtual clock -- common code used by kvm/xen
31 do_div(pv_tsc_khz, src->tsc_to_system_mul); in pvclock_tsc_khz()
32 if (src->tsc_shift < 0) in pvclock_tsc_khz()
33 pv_tsc_khz <<= -src->tsc_shift; in pvclock_tsc_khz()
35 pv_tsc_khz >>= src->tsc_shift; in pvclock_tsc_khz()
61 flags = src->flags; in pvclock_read_flags()
77 flags = src->flags; in pvclock_clocksource_read()
81 src->flags &= ~PVCLOCK_GUEST_STOPPED; in pvclock_clocksource_read()
93 * does not sacrifice accuracy. in pvclock_clocksource_read()
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| /linux-5.10/drivers/video/fbdev/kyro/ |
| D | STG4000InitDevice.c | 41 /* Core clock freq */
44 /* Reference Clock freq */
61 /* PLL Clock */
101 /* Program SD-RAM interface */ in InitSDRAMRegisters()
129 /* Translate clock in Hz */ in ProgramClock()
133 /* Work out acceptable clock in ProgramClock()
134 * The method calculates ~ +- 0.4% (1/256) in ProgramClock()
136 ulMinClock = coreClock - (coreClock >> 8); in ProgramClock()
139 /* Scale clock required for use in calculations */ in ProgramClock()
147 /* loop for pre-divider from min to max */ in ProgramClock()
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| /linux-5.10/Documentation/devicetree/bindings/mfd/ |
| D | rohm,bd70528-pmic.txt | 3 BD70528MWV is an ultra-low quiescent current general purpose, single-chip,
4 power management IC for battery-powered portable devices. The IC
5 integrates 3 ultra-low current consumption buck converters, 3 LDOs and 2
6 LED Drivers. Also included are 4 GPIOs, a real-time clock (RTC), a 32kHz
7 clock gate, high-accuracy VREF for use with an external ADC, flexible
8 dual-input power path, 10 bit SAR ADC for battery temperature monitor and
12 - compatible : Should be "rohm,bd70528"
13 - reg : I2C slave address.
14 - interrupts : The interrupt line the device is connected to.
15 - interrupt-controller : To indicate BD70528 acts as an interrupt controller.
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| /linux-5.10/Documentation/devicetree/bindings/iio/adc/ |
| D | ti,adc12138.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments ADC12138 and similar self-calibrating ADCs
10 - Akinobu Mita <akinobu.mita@gmail.com>
19 - ti,adc12130
20 - ti,adc12132
21 - ti,adc12138
32 description: Conversion clock input.
34 spi-max-frequency: true
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| /linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | lpc32xx-mlc.txt | 4 - compatible: "nxp,lpc3220-mlc"
5 - reg: Address and size of the controller
6 - interrupts: The NAND interrupt specification
7 - gpios: GPIO specification for NAND write protect
11 Hz, to make them independent of actual clock speed and to provide for good
12 accuracy:)
13 - nxp,tcea_delay: TCEA_DELAY
14 - nxp,busy_delay: BUSY_DELAY
15 - nxp,nand_ta: NAND_TA
16 - nxp,rd_high: RD_HIGH
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| /linux-5.10/kernel/time/ |
| D | jiffies.c | 1 // SPDX-License-Identifier: GPL-2.0+
42 * denominator clock source which should function on
49 * for "tick-less" systems.
103 refined_jiffies.name = "refined-jiffies"; in register_refined_jiffies()
108 /* shift_hz stores hz<<8 for extra accuracy */ in register_refined_jiffies()
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| /linux-5.10/include/uapi/linux/ |
| D | rtc.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * This version contains the part of the user interface to the Real Time Clock
6 * Struct rtc_time and first 12 ioctl by Paul Gortmaker, 1996 - separated out
9 * Copyright (C) 1999 Hewlett-Packard Co.
21 * source is self contained, allowing cross-compiles, etc. etc.
53 * +ve pll_value means clock will run faster by
55 * -ve pll_value means clock will run slower by
63 int pll_min; /* max -ve (slower) adjustment value */
65 int pll_negmult; /* factor for -ve correction */
101 #define RTC_VL_ACCURACY_LOW _BITUL(3) /* Voltage is low, RTC accuracy is reduced */
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| /linux-5.10/Documentation/core-api/ |
| D | timekeeping.rst | 10 ------------------------------
13 that return time for different clock references:
56 clocksource without (NTP) adjustments for clock drift. This is
60 -----------------------------------------
92 Return a coarse-grained version of the time as a scalar
93 time64_t. This avoids accessing the clock hardware and rounds
98 -------------------------
117 These are quicker than the non-coarse versions, but less accurate,
125 in a fast path and one still expects better than second accuracy,
127 Skipping the hardware clock access saves around 100 CPU cycles
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| /linux-5.10/drivers/staging/media/atomisp/pci/ |
| D | atomisp_csi2.c | 1 // SPDX-License-Identifier: GPL-2.0
19 #include <media/v4l2-event.h>
20 #include <media/v4l2-mediabus.h>
23 #include "atomisp-regs.h"
34 return v4l2_subdev_get_try_format(&csi2->subdev, cfg, pad); in __csi2_get_format()
36 return &csi2->formats[pad]; in __csi2_get_format()
40 * csi2_enum_mbus_code - Handle pixel format enumeration
44 * return -EINVAL or zero on success
53 while (ic->code) { in csi2_enum_mbus_code()
54 if (i == code->index) { in csi2_enum_mbus_code()
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