| /linux-6.8/arch/riscv/boot/dts/microchip/ |
| D | mpfs.dtsi | 29 clocks = <&clkcfg CLK_CPU>;
58 clocks = <&clkcfg CLK_CPU>;
89 clocks = <&clkcfg CLK_CPU>;
120 clocks = <&clkcfg CLK_CPU>;
151 clocks = <&clkcfg CLK_CPU>;
254 clkcfg: clkcfg@20002000 { label
255 compatible = "microchip,mpfs-clkcfg";
302 clocks = <&clkcfg CLK_MMUART0>;
314 clocks = <&clkcfg CLK_MMUART1>;
326 clocks = <&clkcfg CLK_MMUART2>;
[all …]
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| /linux-6.8/Documentation/devicetree/bindings/clock/ |
| D | microchip,mpfs-clkcfg.yaml | 4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
13 Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
17 user nodes by the CLKCFG node phandle and the clock index in the group, from
22 const: microchip,mpfs-clkcfg
74 clkcfg: clock-controller@20002000 {
75 compatible = "microchip,mpfs-clkcfg";
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| /linux-6.8/drivers/clk/pxa/ |
| D | clk-pxa.c | 136 unsigned int unused, clkcfg; in pxa2xx_core_turbo_switch() local
140 asm("mrc p14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); in pxa2xx_core_turbo_switch()
141 clkcfg &= ~CLKCFG_TURBO & ~CLKCFG_HALFTURBO; in pxa2xx_core_turbo_switch()
143 clkcfg |= CLKCFG_TURBO; in pxa2xx_core_turbo_switch()
144 clkcfg |= CLKCFG_FCS; in pxa2xx_core_turbo_switch()
153 : "=&r" (unused) : "r" (clkcfg)); in pxa2xx_core_turbo_switch()
162 unsigned int clkcfg = freq->clkcfg; in pxa2xx_cpll_change() local
193 /* Set new the CCCR and prepare CLKCFG */ in pxa2xx_cpll_change()
201 " mcr p14, 0, %2, c6, c0, 0 /* set CLKCFG[FCS] */\n" in pxa2xx_cpll_change()
207 : "r" (mdrefr), "r" (clkcfg), "r" (preset_mdrefr), in pxa2xx_cpll_change()
|
| D | clk-pxa27x.c | 169 * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
204 unsigned long clkcfg; in clk_pxa27x_cpll_get_rate() local
209 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); in clk_pxa27x_cpll_get_rate()
210 t = clkcfg & (1 << 0); in clk_pxa27x_cpll_get_rate()
211 ht = clkcfg & (1 << 2); in clk_pxa27x_cpll_get_rate()
301 unsigned long clkcfg; in clk_pxa27x_core_get_parent() local
309 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); in clk_pxa27x_core_get_parent()
310 t = clkcfg & (1 << 0); in clk_pxa27x_core_get_parent()
311 ht = clkcfg & (1 << 2); in clk_pxa27x_core_get_parent()
361 unsigned long clkcfg; in clk_pxa27x_system_bus_get_rate() local
[all …]
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| D | clk-pxa25x.c | 175 unsigned long clkcfg; in clk_pxa25x_core_get_parent() local
178 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); in clk_pxa25x_core_get_parent()
179 t = clkcfg & (1 << 0); in clk_pxa25x_core_get_parent()
218 unsigned long clkcfg, cccr = readl(clk_regs + CCCR); in clk_pxa25x_cpll_get_rate() local
221 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); in clk_pxa25x_cpll_get_rate()
222 t = clkcfg & (1 << 0); in clk_pxa25x_cpll_get_rate()
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| D | clk-pxa.h | 141 unsigned int clkcfg; member
|
| /linux-6.8/Documentation/devicetree/bindings/rtc/ |
| D | microchip,mfps-rtc.yaml | 63 clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
|
| /linux-6.8/Documentation/devicetree/bindings/net/can/ |
| D | microchip,mpfs-can.yaml | 42 clocks = <&clkcfg 17>;
|
| /linux-6.8/Documentation/devicetree/bindings/usb/ |
| D | microchip,mpfs-musb.yaml | 52 clocks = <&clkcfg CLK_USB>;
|
| /linux-6.8/Documentation/devicetree/bindings/spi/ |
| D | microchip,mpfs-spi.yaml | 54 clocks = <&clkcfg CLK_SPI0>;
|
| /linux-6.8/Documentation/devicetree/bindings/i2c/ |
| D | microchip,corei2c.yaml | 51 clocks = <&clkcfg 15>;
|
| /linux-6.8/drivers/clk/ralink/ |
| D | clk-mt7621.c | 261 u32 clkcfg, clk_sel, curclk, ffiv, ffrac; in mt7621_cpu_recalc_rate() local
265 regmap_read(sysc, SYSC_REG_CLKCFG0, &clkcfg); in mt7621_cpu_recalc_rate()
266 clk_sel = FIELD_GET(CPU_CLK_SEL_MASK, clkcfg); in mt7621_cpu_recalc_rate()
|
| /linux-6.8/Documentation/devicetree/bindings/gpio/ |
| D | microchip,mpfs-gpio.yaml | 82 clocks = <&clkcfg 25>;
|
| /linux-6.8/Documentation/devicetree/bindings/pwm/ |
| D | microchip,corepwm.yaml | 80 clocks = <&clkcfg 30>;
|
| /linux-6.8/arch/arm/mach-pxa/ |
| D | sleep.S | 74 mov r0, #0x2 @ prepare value for CLKCFG
|
| /linux-6.8/drivers/clk/microchip/ |
| D | clk-mpfs.c | 486 { .compatible = "microchip,mpfs-clkcfg", },
494 .name = "microchip-mpfs-clkcfg",
|
| /linux-6.8/drivers/gpu/drm/i915/gt/ |
| D | intel_gt_clock_utils.c | 150 * (“CLKCFG”) MCHBAR register) in gen4_read_clock_frequency()
|
| /linux-6.8/drivers/gpu/drm/i915/ |
| D | intel_mchbar_regs.h | 51 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) macro
|
| /linux-6.8/drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 3405 u32 clkcfg; in i9xx_hrawclk() local
3417 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; in i9xx_hrawclk()
3420 switch (clkcfg) { in i9xx_hrawclk()
3434 MISSING_CASE(clkcfg); in i9xx_hrawclk()
3438 switch (clkcfg) { in i9xx_hrawclk()
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| /linux-6.8/drivers/gpu/drm/i915/soc/ |
| D | intel_dram.c | 50 tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG); in pnv_detect_mem_freq()
|