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/linux-5.10/drivers/clk/meson/
Dclk-phase.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
11 #include "clk-phase.h"
16 meson_clk_phase_data(struct clk_regmap *clk) in meson_clk_phase_data() argument
18 return (struct meson_clk_phase_data *)clk->data; in meson_clk_phase_data()
39 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_phase_get_phase() local
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
45 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
4 obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
5 obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
6 obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
7 obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o
8 obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
9 obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
10 obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
11 obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
12 obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
[all …]
/linux-5.10/drivers/clk/sunxi/
Dclk-mod0.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
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/linux-5.10/drivers/mmc/host/
Dsdhci-sirf.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/mmc/slot-gpio.h>
14 #include "sdhci-pltfm.h"
29 * 8bit-width enable bit of CSR SD hosts is 3, in sdhci_sirf_set_bus_width()
42 u32 val = readl(host->ioaddr + reg); in sdhci_sirf_readl_le()
45 (host->mmc->caps & MMC_CAP_UHS_SDR50))) { in sdhci_sirf_readl_le()
64 ret = readw(host->ioaddr + reg); in sdhci_sirf_readw_le()
67 ret = readw(host->ioaddr + SDHCI_HOST_VERSION); in sdhci_sirf_readw_le()
77 int phase; in sdhci_sirf_execute_tuning() local
80 int start = -1, end = 0, tuning_value = -1, range = 0; in sdhci_sirf_execute_tuning()
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Dmmci_stm32_sdmmc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/dma-mapping.h>
64 for_each_sg(data->sg, sg, data->sg_len - 1, i) { in sdmmc_idma_validate_data()
65 if (!IS_ALIGNED(data->sg->offset, sizeof(u32)) || in sdmmc_idma_validate_data()
66 !IS_ALIGNED(data->sg->length, SDMMC_IDMA_BURST)) { in sdmmc_idma_validate_data()
67 dev_err(mmc_dev(host->mmc), in sdmmc_idma_validate_data()
69 data->sg->offset, data->sg->length); in sdmmc_idma_validate_data()
70 return -EINVAL; in sdmmc_idma_validate_data()
74 if (!IS_ALIGNED(data->sg->offset, sizeof(u32))) { in sdmmc_idma_validate_data()
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Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-pltfm.h"
55 * On some SoCs the syscon area has a feature where the upper 16-bits of
56 * each 32-bit register act as a write mask for the lower 16-bits. This allows
64 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
68 * @shift: Bit offset within @reg of this field (or -1 if not avail)
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Dsdhci-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
20 #include "sdhci-pltfm.h"
119 #define INVALID_TUNING_PHASE -1
133 /* Max load for eMMC Vdd-io supply */
137 msm_host->var_ops->msm_readl_relaxed(host, offset)
140 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
260 struct clk *bus_clk; /* SDHC bus voter clock */
261 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
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Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
21 struct clk *drv_clk;
22 struct clk *sample_clk;
29 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_set_ios()
34 if (ios->clock == 0) in dw_mci_rk3288_set_ios()
41 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) in dw_mci_rk3288_set_ios()
44 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
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/linux-5.10/include/trace/events/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #define TRACE_SYSTEM clk
15 DECLARE_EVENT_CLASS(clk,
22 __string( name, core->name )
26 __assign_str(name, core->name);
32 DEFINE_EVENT(clk, clk_enable,
39 DEFINE_EVENT(clk, clk_enable_complete,
46 DEFINE_EVENT(clk, clk_disable,
53 DEFINE_EVENT(clk, clk_disable_complete,
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/linux-5.10/drivers/clk/rockchip/
Dclk-mmc-phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
12 #include "clk.h"
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
54 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_phase()
58 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
86 * MMC host to the card, which expects the phase clock inherits in rockchip_mmc_set_phase()
97 pr_err("%s: invalid clk rate\n", __func__); in rockchip_mmc_set_phase()
98 return -EINVAL; in rockchip_mmc_set_phase()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
8 clk-rockchip-y += clk.o
9 clk-rockchip-y += clk-pll.o
10 clk-rockchip-y += clk-cpu.o
11 clk-rockchip-y += clk-half-divider.o
12 clk-rockchip-y += clk-inverter.o
13 clk-rockchip-y += clk-mmc-phase.o
14 clk-rockchip-y += clk-muxgrf.o
15 clk-rockchip-y += clk-ddr.o
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Dclk-inverter.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
11 #include "clk.h"
30 val = readl(inv_clock->reg) >> inv_clock->shift; in rockchip_inv_get_phase()
43 pr_err("%s: unsupported phase %d for %s\n", in rockchip_inv_set_phase()
45 return -EINVAL; in rockchip_inv_set_phase()
48 if (inv_clock->flags & ROCKCHIP_INVERTER_HIWORD_MASK) { in rockchip_inv_set_phase()
49 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), in rockchip_inv_set_phase()
50 inv_clock->reg); in rockchip_inv_set_phase()
55 spin_lock_irqsave(inv_clock->lock, flags); in rockchip_inv_set_phase()
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/linux-5.10/drivers/clk/hisilicon/
Dclk-hisi-phase.c1 // SPDX-License-Identifier: GPL-2.0
5 * Simple HiSilicon phase clock implementation.
14 #include "clk.h"
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
39 return -EINVAL; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o
8 obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
9 obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
10 obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
11 obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
12 obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
13 obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
14 obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o
15 obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
[all …]
/linux-5.10/Documentation/devicetree/bindings/clock/
Daltr_socfpga.txt5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
18 - #clock-cells : from common clock binding, shall be set to 0.
21 - fixed-divider : If clocks have a fixed divider value, use this property.
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
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/linux-5.10/drivers/clk/
Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
81 int phase; member
95 #include <trace/events/clk.h>
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/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dccg.c36 (dccg_dcn->regs->reg)
40 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
43 dccg_dcn->base.ctx
45 dccg->ctx->logger
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
53 int modulo, phase; in dccg2_update_dpp_dto() local
55 // phase / modulo = dpp pipe clk / dpp global clk in dccg2_update_dpp_dto()
57 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg2_update_dpp_dto()
59 if (phase > 0xff) { in dccg2_update_dpp_dto()
[all …]
/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-samsung.txt8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
18 - interrupts: The interrupt number to the cpu. The interrupt specifier format
21 - dmas : Two or more DMA channel specifiers following the convention outlined
24 - dma-names: Names for the dma channels. There must be at least one channel
[all …]
/linux-5.10/Documentation/devicetree/bindings/iio/frequency/
Dadf4350.txt4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
21 - adi,reference-div2-enable: Enables reference divider.
[all …]
/linux-5.10/drivers/clk/sunxi-ng/
Dccu_phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
32 return -EINVAL; in ccu_phase_get_phase()
37 return -EINVAL; in ccu_phase_get_phase()
42 return -EINVAL; in ccu_phase_get_phase()
[all …]
/linux-5.10/include/linux/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/clk.h
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
17 struct clk;
22 * DOC: clk notifier callback types
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
32 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
35 * POST_RATE_CHANGE - called after the clk rate change has successfully
44 * struct clk_notifier - associate a clk with a notifier
45 * @clk: struct clk * to associate the notifier with
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/linux-5.10/drivers/clk/qcom/
Dclk-alpha-pll.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
8 #include "clk-regmap.h"
57 * struct clk_alpha_pll - phase locked loop (PLL)
78 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
81 * @width: width of post-divider
82 * @post_div_shift: shift to differentiate between odd & even post-divider
83 * @post_div_table: table with PLL odd and even post-divider settings
84 * @num_post_div: Number of PLL post-divider settings
Dclk-pll.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
13 * struct pll_freq_tbl - PLL frequency table
28 * struct clk_pll - phase locked loop (PLL)
37 * @hw: handle between common and hardware-specific interfaces
/linux-5.10/drivers/scsi/
Dinitio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 1994-1998 Initio Corporation
14 * This is the Linux low-level SCSI driver for Initio INI-9X00U/UW SCSI host
17 * 08/06/97 hc - v1.01h
18 * - Support inic-940 and inic-935
19 * 09/26/97 hc - v1.01i
20 * - Make correction from J.W. Schultz suggestion
21 * 10/13/97 hc - Support reset function
22 * 10/21/97 hc - v1.01j
23 * - Support 32 LUN (SCSI 3)
[all …]
/linux-5.10/sound/soc/codecs/
Dsirf-audio-codec.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/clk.h>
25 #include "sirf-audio-codec.h"
28 struct clk *clk; member
33 static const char * const input_mode_mux[] = {"Single-ended",
42 static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -12400, 100, 0);
45 0, 7, TLV_DB_SCALE_ITEM(-100, 100, 0),
122 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in atlas6_codec_enable_and_reset_event()
126 enable_and_reset_codec(sirf_audio_codec->regmap, in atlas6_codec_enable_and_reset_event()
130 regmap_update_bits(sirf_audio_codec->regmap, in atlas6_codec_enable_and_reset_event()
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