Lines Matching +full:clk +full:- +full:phase +full:-
1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
21 struct clk *drv_clk;
22 struct clk *sample_clk;
29 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_set_ios()
34 if (ios->clock == 0) in dw_mci_rk3288_set_ios()
41 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) in dw_mci_rk3288_set_ios()
44 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
46 if (ios->bus_width == MMC_BUS_WIDTH_8 && in dw_mci_rk3288_set_ios()
47 ios->timing == MMC_TIMING_MMC_DDR52) in dw_mci_rk3288_set_ios()
48 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()
50 cclkin = ios->clock * RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()
52 ret = clk_set_rate(host->ciu_clk, cclkin); in dw_mci_rk3288_set_ios()
54 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); in dw_mci_rk3288_set_ios()
56 bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()
57 if (bus_hz != host->bus_hz) { in dw_mci_rk3288_set_ios()
58 host->bus_hz = bus_hz; in dw_mci_rk3288_set_ios()
60 host->current_speed = 0; in dw_mci_rk3288_set_ios()
64 if (!IS_ERR(priv->sample_clk)) in dw_mci_rk3288_set_ios()
65 clk_set_phase(priv->sample_clk, priv->default_sample_phase); in dw_mci_rk3288_set_ios()
68 * Set the drive phase offset based on speed mode to achieve hold times. in dw_mci_rk3288_set_ios()
93 if (!IS_ERR(priv->drv_clk)) { in dw_mci_rk3288_set_ios()
94 int phase; in dw_mci_rk3288_set_ios() local
97 * In almost all cases a 90 degree phase offset will provide in dw_mci_rk3288_set_ios()
102 phase = 90; in dw_mci_rk3288_set_ios()
104 switch (ios->timing) { in dw_mci_rk3288_set_ios()
108 * bus width is 8 we need to double the phase offset in dw_mci_rk3288_set_ios()
111 if (ios->bus_width == MMC_BUS_WIDTH_8) in dw_mci_rk3288_set_ios()
112 phase = 180; in dw_mci_rk3288_set_ios()
124 phase = 180; in dw_mci_rk3288_set_ios()
128 clk_set_phase(priv->drv_clk, phase); in dw_mci_rk3288_set_ios()
137 struct dw_mci *host = slot->host; in dw_mci_rk3288_execute_tuning()
138 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_execute_tuning()
139 struct mmc_host *mmc = slot->mmc; in dw_mci_rk3288_execute_tuning()
149 int longest_range_len = -1; in dw_mci_rk3288_execute_tuning()
150 int longest_range = -1; in dw_mci_rk3288_execute_tuning()
153 if (IS_ERR(priv->sample_clk)) { in dw_mci_rk3288_execute_tuning()
154 dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n"); in dw_mci_rk3288_execute_tuning()
155 return -EIO; in dw_mci_rk3288_execute_tuning()
158 ranges = kmalloc_array(priv->num_phases / 2 + 1, in dw_mci_rk3288_execute_tuning()
161 return -ENOMEM; in dw_mci_rk3288_execute_tuning()
163 /* Try each phase and extract good ranges */ in dw_mci_rk3288_execute_tuning()
164 for (i = 0; i < priv->num_phases; ) { in dw_mci_rk3288_execute_tuning()
165 clk_set_phase(priv->sample_clk, in dw_mci_rk3288_execute_tuning()
166 TUNING_ITERATION_TO_PHASE(i, priv->num_phases)); in dw_mci_rk3288_execute_tuning()
175 ranges[range_count-1].start = i; in dw_mci_rk3288_execute_tuning()
178 ranges[range_count-1].end = i; in dw_mci_rk3288_execute_tuning()
180 } else if (i == priv->num_phases - 1) { in dw_mci_rk3288_execute_tuning()
189 i += DIV_ROUND_UP(20 * priv->num_phases, 360); in dw_mci_rk3288_execute_tuning()
192 if (i >= priv->num_phases) in dw_mci_rk3288_execute_tuning()
193 i = priv->num_phases - 1; in dw_mci_rk3288_execute_tuning()
200 dev_warn(host->dev, "All phases bad!"); in dw_mci_rk3288_execute_tuning()
201 ret = -EIO; in dw_mci_rk3288_execute_tuning()
207 ranges[0].start = ranges[range_count-1].start; in dw_mci_rk3288_execute_tuning()
208 range_count--; in dw_mci_rk3288_execute_tuning()
211 if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) { in dw_mci_rk3288_execute_tuning()
212 clk_set_phase(priv->sample_clk, priv->default_sample_phase); in dw_mci_rk3288_execute_tuning()
213 dev_info(host->dev, "All phases work, using default phase %d.", in dw_mci_rk3288_execute_tuning()
214 priv->default_sample_phase); in dw_mci_rk3288_execute_tuning()
220 int len = (ranges[i].end - ranges[i].start + 1); in dw_mci_rk3288_execute_tuning()
223 len += priv->num_phases; in dw_mci_rk3288_execute_tuning()
230 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n", in dw_mci_rk3288_execute_tuning()
232 priv->num_phases), in dw_mci_rk3288_execute_tuning()
234 priv->num_phases), in dw_mci_rk3288_execute_tuning()
239 dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n", in dw_mci_rk3288_execute_tuning()
241 priv->num_phases), in dw_mci_rk3288_execute_tuning()
243 priv->num_phases), in dw_mci_rk3288_execute_tuning()
248 middle_phase %= priv->num_phases; in dw_mci_rk3288_execute_tuning()
249 dev_info(host->dev, "Successfully tuned phase to %d\n", in dw_mci_rk3288_execute_tuning()
250 TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases)); in dw_mci_rk3288_execute_tuning()
252 clk_set_phase(priv->sample_clk, in dw_mci_rk3288_execute_tuning()
254 priv->num_phases)); in dw_mci_rk3288_execute_tuning()
263 struct device_node *np = host->dev->of_node; in dw_mci_rk3288_parse_dt()
266 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); in dw_mci_rk3288_parse_dt()
268 return -ENOMEM; in dw_mci_rk3288_parse_dt()
270 if (of_property_read_u32(np, "rockchip,desired-num-phases", in dw_mci_rk3288_parse_dt()
271 &priv->num_phases)) in dw_mci_rk3288_parse_dt()
272 priv->num_phases = 360; in dw_mci_rk3288_parse_dt()
274 if (of_property_read_u32(np, "rockchip,default-sample-phase", in dw_mci_rk3288_parse_dt()
275 &priv->default_sample_phase)) in dw_mci_rk3288_parse_dt()
276 priv->default_sample_phase = 0; in dw_mci_rk3288_parse_dt()
278 priv->drv_clk = devm_clk_get(host->dev, "ciu-drive"); in dw_mci_rk3288_parse_dt()
279 if (IS_ERR(priv->drv_clk)) in dw_mci_rk3288_parse_dt()
280 dev_dbg(host->dev, "ciu-drive not available\n"); in dw_mci_rk3288_parse_dt()
282 priv->sample_clk = devm_clk_get(host->dev, "ciu-sample"); in dw_mci_rk3288_parse_dt()
283 if (IS_ERR(priv->sample_clk)) in dw_mci_rk3288_parse_dt()
284 dev_dbg(host->dev, "ciu-sample not available\n"); in dw_mci_rk3288_parse_dt()
286 host->priv = priv; in dw_mci_rk3288_parse_dt()
294 host->sdio_id0 = 8; in dw_mci_rockchip_init()
296 if (of_device_is_compatible(host->dev->of_node, in dw_mci_rockchip_init()
297 "rockchip,rk3288-dw-mshc")) in dw_mci_rockchip_init()
298 host->bus_hz /= RK3288_CLKGEN_DIV; in dw_mci_rockchip_init()
325 { .compatible = "rockchip,rk2928-dw-mshc",
327 { .compatible = "rockchip,rk3288-dw-mshc",
339 if (!pdev->dev.of_node) in dw_mci_rockchip_probe()
340 return -ENODEV; in dw_mci_rockchip_probe()
342 match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node); in dw_mci_rockchip_probe()
343 drv_data = match->data; in dw_mci_rockchip_probe()
345 pm_runtime_get_noresume(&pdev->dev); in dw_mci_rockchip_probe()
346 pm_runtime_set_active(&pdev->dev); in dw_mci_rockchip_probe()
347 pm_runtime_enable(&pdev->dev); in dw_mci_rockchip_probe()
348 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in dw_mci_rockchip_probe()
349 pm_runtime_use_autosuspend(&pdev->dev); in dw_mci_rockchip_probe()
353 pm_runtime_disable(&pdev->dev); in dw_mci_rockchip_probe()
354 pm_runtime_set_suspended(&pdev->dev); in dw_mci_rockchip_probe()
355 pm_runtime_put_noidle(&pdev->dev); in dw_mci_rockchip_probe()
359 pm_runtime_put_autosuspend(&pdev->dev); in dw_mci_rockchip_probe()
366 pm_runtime_get_sync(&pdev->dev); in dw_mci_rockchip_remove()
367 pm_runtime_disable(&pdev->dev); in dw_mci_rockchip_remove()
368 pm_runtime_put_noidle(&pdev->dev); in dw_mci_rockchip_remove()
394 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
395 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");