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/qemu/rust/qemu-api/src/
H A Derror.rs54 cause: Option<anyhow::Error>, field
61 self.cause.as_ref().map(AsRef::as_ref) in source()
68 .or_else(|| self.cause.as_deref().map(std::error::Error::description)) in description()
69 .expect("no message nor cause?") in description()
80 if let Some(ref cause) = self.cause { in fmt()
81 write!(f, "{prefix}{cause}")?; in fmt()
83 panic!("no message nor cause?"); in fmt()
95 cause: None, in from()
108 cause: None, in from()
121 cause: Some(error), in from()
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/qemu/target/xtensa/
H A Dexc_helper.c47 void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause) in HELPER()
64 env->sregs[EXCCAUSE] = cause; in HELPER()
71 uint32_t pc, uint32_t cause, uint32_t vaddr) in HELPER()
74 HELPER(exception_cause)(env, pc, cause); in HELPER()
77 void debug_exception_env(CPUXtensaState *env, uint32_t cause) in debug_exception_env() argument
80 HELPER(debug_exception)(env, env->pc, cause); in debug_exception_env()
84 void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause) in HELPER()
89 env->sregs[DEBUGCAUSE] = cause; in HELPER()
158 * exception with the 'level-1 interrupt' exception cause.
H A Dhelper.c226 uint32_t cause; in xtensa_breakpoint_handler() local
229 cause = check_hw_breakpoints(env); in xtensa_breakpoint_handler()
230 if (cause) { in xtensa_breakpoint_handler()
231 debug_exception_env(env, cause); in xtensa_breakpoint_handler()
/qemu/target/mips/tcg/system/
H A Dtlb_helper.c583 * Synchronous exceptions detected on memory accesses cause a silent exit
1036 int cause = -1; in mips_cpu_do_interrupt() local
1132 cause = 0; in mips_cpu_do_interrupt()
1164 cause = 1; in mips_cpu_do_interrupt()
1168 cause = 2; in mips_cpu_do_interrupt()
1189 cause = 3; in mips_cpu_do_interrupt()
1210 cause = 4; in mips_cpu_do_interrupt()
1214 cause = 5; in mips_cpu_do_interrupt()
1218 cause = 6; in mips_cpu_do_interrupt()
1221 cause = 7; in mips_cpu_do_interrupt()
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/qemu/target/ppc/
H A Dmisc_helper.c90 const char *caller, uint32_t cause, in raise_hv_fu_exception() argument
98 raise_exception_err_ra(env, POWERPC_EXCP_HV_FU, cause, raddr); in raise_hv_fu_exception()
102 uint32_t sprn, uint32_t cause, in raise_fu_exception() argument
108 cause &= FSCR_IC_MASK; in raise_fu_exception()
109 env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS; in raise_fu_exception()
116 const char *caller, uint32_t cause) in helper_hfscr_facility_check() argument
121 raise_hv_fu_exception(env, bit, caller, cause, GETPC()); in helper_hfscr_facility_check()
127 uint32_t sprn, uint32_t cause) in helper_fscr_facility_check() argument
134 raise_fu_exception(env, bit, sprn, cause, GETPC()); in helper_fscr_facility_check()
139 uint32_t sprn, uint32_t cause) in helper_msr_facility_check() argument
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H A Dmmu-radix64.c145 vaddr eaddr, uint32_t cause) in ppc_radix64_raise_si() argument
150 qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx" cause %08x\n", in ppc_radix64_raise_si()
152 eaddr, cause); in ppc_radix64_raise_si()
158 env->error_code = cause; in ppc_radix64_raise_si()
161 cause |= DSISR_ISSTORE; in ppc_radix64_raise_si()
166 env->spr[SPR_DSISR] = cause; in ppc_radix64_raise_si()
176 vaddr eaddr, hwaddr g_raddr, uint32_t cause) in ppc_radix64_raise_hsi() argument
182 if (cause & DSISR_PRTABLE_FAULT) { in ppc_radix64_raise_hsi()
189 HWADDR_PRIx" cause %08x\n", in ppc_radix64_raise_hsi()
191 eaddr, g_raddr, cause); in ppc_radix64_raise_hsi()
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/qemu/target/riscv/
H A Dcpu_helper.c2125 /* if no promotion, return original cause */ in promote_load_fault()
2129 static void riscv_do_nmi(CPURISCVState *env, target_ulong cause, bool virt) in riscv_do_nmi() argument
2134 env->mncause = cause; in riscv_do_nmi()
2165 * so we mask off the MSB and separate into trap type and cause. in riscv_cpu_do_interrupt()
2168 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; in riscv_cpu_do_interrupt() local
2170 bool s_injected = env->mvip & (1ULL << cause) & env->mvien && in riscv_cpu_do_interrupt()
2171 !(env->mip & (1ULL << cause)); in riscv_cpu_do_interrupt()
2172 bool vs_injected = env->hvip & (1ULL << cause) & env->hvien && in riscv_cpu_do_interrupt()
2173 !(env->mip & (1ULL << cause)); in riscv_cpu_do_interrupt()
2188 riscv_do_nmi(env, cause | ((target_ulong)1U << (mxlen - 1)), in riscv_cpu_do_interrupt()
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H A Dtrace-events2 …4_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRI…
/qemu/tests/tcg/multiarch/
H A Dsegfault.c4 /* Cause a segfault for testing purposes. */
11 /* Cause segfault. */ in main()
/qemu/target/rx/
H A Dop_helper.c74 int xcpt, cause, enable; in update_fpsw() local
81 /* Clear the cause entries */ in update_fpsw()
82 env->fpsw = FIELD_DP32(env->fpsw, FPSW, CAUSE, 0); in update_fpsw()
113 cause = FIELD_EX32(env->fpsw, FPSW, CAUSE); in update_fpsw()
116 if (cause & enable) { in update_fpsw()
/qemu/replay/
H A Dreplay.c73 static const char *replay_shutdown_event_name(ShutdownCause cause) in replay_shutdown_event_name() argument
75 switch (cause) { in replay_shutdown_event_name()
264 void replay_shutdown_request(ShutdownCause cause) in replay_shutdown_request() argument
268 replay_put_event(EVENT_SHUTDOWN + cause); in replay_shutdown_request()
299 * and cause the recursion. in replay_async_events()
/qemu/hw/net/
H A De1000_regs.h116 #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
117 #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
118 #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
119 #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
120 #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
121 #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
H A Digb_regs.h310 /* Extended Interrupt Cause Read */
319 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
321 /* Extended Interrupt Cause Set */
386 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
388 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
427 #define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */
439 #define E1000_LVMMC 0x03548 /* Last VM Misbehavior cause */
643 /* Mirror Extended Interrupt Cause Set; WO */
676 /* Mirror Extended Interrupt Cause Set; RC/W1C */
/qemu/python/qemu/qmp/
H A Dprotocol.py76 This Exception always wraps a "root cause" exception that can be
80 :param exc: The root-cause exception.
86 #: Wrapped root cause exception
90 cause = str(self.exc)
91 if not cause:
93 cause = exception_summary(self.exc)
94 return f"{self.error_message}: {cause}"
454 # cause in greater detail.
700 the one that occurred first; presuming it to be the root cause
784 # This *may* cause an error and force us over into the error path.
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/qemu/hw/riscv/
H A Dtrace-events13 riscv_iommu_notify_int_vector(uint32_t cause, uint32_t vector) "Interrupt cause 0x%x sent via vecto…
/qemu/target/riscv/insn_trans/
H A Dtrans_rvi.c.inc1053 * If rd == 0, the insn shall not read the csr, nor cause any of the
1068 * If rd == 0, the insn shall not read the csr, nor cause any of the
1084 * cause any of the side effects that might occur on a csr write.
1087 * unmodified value back to the csr and will cause side effects.
1113 * cause any of the side effects that might occur on a csr write.
1116 * unmodified value back to the csr and will cause side effects.
1144 * If rd == 0, the insn shall not read the csr, nor cause any of the
1158 * If rd == 0, the insn shall not read the csr, nor cause any of the
1174 * cause any of the side effects that might occur on a csr write.
1177 * unmodified value back to the csr and will cause side effects.
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/qemu/target/loongarch/
H A Dcpu.h46 #define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */
53 FIELD(FCSR0, CAUSE, 24, 5)
55 #define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE)
58 (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \
62 (REG) |= FIELD_DP32(0, FCSR0, CAUSE, V); \
H A Dcpu.c171 int cause = -1; in loongarch_cpu_do_interrupt() local
202 cause = cs->exception_index; in loongarch_cpu_do_interrupt()
223 cause = cs->exception_index; in loongarch_cpu_do_interrupt()
249 EXCODE_MCODE(cause)); in loongarch_cpu_do_interrupt()
251 EXCODE_SUBCODE(cause)); in loongarch_cpu_do_interrupt()
278 " cause %d\n" " A " TARGET_FMT_lx " D " in loongarch_cpu_do_interrupt()
282 cause, env->CSR_BADV, env->CSR_DERA, vector, in loongarch_cpu_do_interrupt()
288 set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); in loongarch_cpu_do_interrupt()
292 " cause %d%s\n, ESTAT " TARGET_FMT_lx in loongarch_cpu_do_interrupt()
297 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, in loongarch_cpu_do_interrupt()
/qemu/include/system/
H A Drunstate.h46 static inline bool shutdown_caused_by_guest(ShutdownCause cause) in shutdown_caused_by_guest() argument
48 return cause >= SHUTDOWN_CAUSE_GUEST_SHUTDOWN; in shutdown_caused_by_guest()
/qemu/docs/devel/
H A Dtcg-icount.rst41 translated block and will cause a return to the outer loop to deal
46 would cause the instruction budget to go negative we exit the main
/qemu/tests/tcg/aarch64/system/
H A Dmte.S56 * TCF[41:40] = 0b01 => Tag Check Faults cause a synchronous exception
99 * not cause any Tag Check Fault since logical tag in tagged_addr and
/qemu/hw/s390x/
H A Dtod.c67 "which could cause the guest to hang."); in s390_tod_save()
86 "cause the guest to hang."); in s390_tod_load()
/qemu/include/hw/
H A Dptimer.h32 * bug in the QEMU device and will cause warning messages to be printed
90 * (though it will cause a reload). Only a counter decrement to "0"
91 * will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER;
292 * Note that this can cause it to "lose" time, even if it is immediately
/qemu/target/alpha/
H A Dhelper.c131 target_ulong mmcsr, cause; in alpha_cpu_record_sigsegv() local
137 cause = 0; in alpha_cpu_record_sigsegv()
141 cause = 1; in alpha_cpu_record_sigsegv()
145 cause = -1; in alpha_cpu_record_sigsegv()
163 env->trap_arg2 = cause; in alpha_cpu_record_sigsegv()
/qemu/docs/devel/migration/
H A Dpostcopy.rst13 transferred, and accesses to pages that are yet to be transferred cause
32 will now cause the transition from precopy to postcopy.
79 during the postcopy phase, and to cause any huge pages that
110 Loading of device data may cause the device emulation to access guest RAM

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