Home
last modified time | relevance | path

Searched full:cap (Results 1 – 25 of 147) sorted by relevance

123456

/qemu/tests/qemu-iotests/tests/
H A Dzoned.out5 start: 0x0, len 0x80000, cap 0x80000, wptr 0x0, zcond:1, [type: 2]
8 start: 0x0, len 0x80000, cap 0x80000, wptr 0x0, zcond:1, [type: 2]
9 start: 0x80000, len 0x80000, cap 0x80000, wptr 0x80000, zcond:1, [type: 2]
10 start: 0x100000, len 0x80000, cap 0x80000, wptr 0x100000, zcond:1, [type: 2]
11 start: 0x180000, len 0x80000, cap 0x80000, wptr 0x180000, zcond:1, [type: 2]
12 start: 0x200000, len 0x80000, cap 0x80000, wptr 0x200000, zcond:1, [type: 2]
13 start: 0x280000, len 0x80000, cap 0x80000, wptr 0x280000, zcond:1, [type: 2]
14 start: 0x300000, len 0x80000, cap 0x80000, wptr 0x300000, zcond:1, [type: 2]
15 start: 0x380000, len 0x80000, cap 0x80000, wptr 0x380000, zcond:1, [type: 2]
16 start: 0x400000, len 0x80000, cap 0x80000, wptr 0x400000, zcond:1, [type: 2]
[all …]
/qemu/hw/ppc/
H A Dspapr_caps.c76 SpaprCapabilityInfo *cap = opaque; in spapr_cap_get_bool() local
78 bool value = spapr_get_cap(spapr, cap->index) == SPAPR_CAP_ON; in spapr_cap_get_bool()
86 SpaprCapabilityInfo *cap = opaque; in spapr_cap_set_bool() local
94 spapr->cmd_line_caps[cap->index] = true; in spapr_cap_set_bool()
95 spapr->eff.caps[cap->index] = value ? SPAPR_CAP_ON : SPAPR_CAP_OFF; in spapr_cap_set_bool()
102 SpaprCapabilityInfo *cap = opaque; in spapr_cap_get_string() local
105 uint8_t value = spapr_get_cap(spapr, cap->index); in spapr_cap_get_string()
107 if (value >= cap->possible->num) { in spapr_cap_get_string()
108 error_setg(errp, "Invalid value (%d) for cap-%s", value, cap->name); in spapr_cap_get_string()
112 val = g_strdup(cap->possible->vals[value]); in spapr_cap_get_string()
[all …]
/qemu/hw/s390x/
H A Ds390-pci-vfio.c110 struct vfio_device_info_cap_zpci_base *cap; in s390_pci_read_base() local
122 cap = (void *) hdr; in s390_pci_read_base()
124 pbdev->zpci_fn.sdma = cap->start_dma; in s390_pci_read_base()
125 pbdev->zpci_fn.edma = cap->end_dma; in s390_pci_read_base()
126 pbdev->zpci_fn.pchid = cap->pchid; in s390_pci_read_base()
127 pbdev->zpci_fn.vfn = cap->vfn; in s390_pci_read_base()
128 pbdev->zpci_fn.pfgid = cap->gid; in s390_pci_read_base()
133 pbdev->pft = cap->pft; in s390_pci_read_base()
154 if (vfio_size > 0 && vfio_size < cap->end_dma - cap->start_dma + 1) { in s390_pci_read_base()
155 pbdev->zpci_fn.edma = cap->start_dma + vfio_size - 1; in s390_pci_read_base()
[all …]
/qemu/hw/pci/
H A Dslotid_cap.c15 int cap; in slotid_cap_init() local
27 cap = pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, in slotid_cap_init()
29 if (cap < 0) { in slotid_cap_init()
30 return cap; in slotid_cap_init()
33 d->config[cap + PCI_SID_ESR] = PCI_SID_ESR_FIC | in slotid_cap_init()
35 d->cmask[cap + PCI_SID_ESR] = 0xff; in slotid_cap_init()
36 d->config[cap + PCI_SID_CHASSIS_NR] = chassis; in slotid_cap_init()
40 d->wmask[cap + PCI_SID_CHASSIS_NR] = 0xff; in slotid_cap_init()
H A Dpcie_doe.c101 doe_cap->cap.intr = intr; in pcie_doe_init()
102 doe_cap->cap.vec = vec; in pcie_doe_init()
169 if (doe_cap->cap.intr && doe_cap->ctrl.intr) { in pcie_doe_irq_assert()
176 msix_notify(dev, doe_cap->cap.vec); in pcie_doe_irq_assert()
178 msi_notify(dev, doe_cap->cap.vec); in pcie_doe_irq_assert()
265 doe_cap->cap.intr); in pcie_doe_read_config()
267 doe_cap->cap.vec); in pcie_doe_read_config()
/qemu/target/i386/hvf/
H A Dx86_cpuid.c61 uint64_t cap; in hvf_get_supported_cpuid() local
106 hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap); in hvf_get_supported_cpuid()
107 if (!(cap & CPU_BASED2_INVPCID)) { in hvf_get_supported_cpuid()
131 hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap); in hvf_get_supported_cpuid()
133 if (!(cap & CPU_BASED2_XSAVES_XRSTORS)) { in hvf_get_supported_cpuid()
146 hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap); in hvf_get_supported_cpuid()
147 if (!(cap2ctrl(cap, CPU_BASED2_RDTSCP) & CPU_BASED2_RDTSCP)) { in hvf_get_supported_cpuid()
150 hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &cap); in hvf_get_supported_cpuid()
151 if (!(cap2ctrl(cap, CPU_BASED_TSC_OFFSET) & CPU_BASED_TSC_OFFSET)) { in hvf_get_supported_cpuid()
/qemu/audio/
H A Daudio.c156 void AUD_vlog (const char *cap, const char *fmt, va_list ap) in AUD_vlog() argument
158 if (cap) { in AUD_vlog()
159 fprintf(stderr, "%s: ", cap); in AUD_vlog()
165 void AUD_log (const char *cap, const char *fmt, ...) in AUD_log() argument
170 AUD_vlog (cap, fmt, ap); in AUD_log()
391 CaptureVoiceOut *cap; in audio_pcm_capture_find_specific() local
393 for (cap = s->cap_head.lh_first; cap; cap = cap->entries.le_next) { in audio_pcm_capture_find_specific()
394 if (audio_pcm_info_eq (&cap->hw.info, as)) { in audio_pcm_capture_find_specific()
395 return cap; in audio_pcm_capture_find_specific()
401 static void audio_notify_capture (CaptureVoiceOut *cap, audcnotification_e cmd) in audio_notify_capture() argument
[all …]
H A Dwavcapture.c14 CaptureVoiceOut *cap; member
88 AUD_del_capture (wav->cap, wav); in wav_capture_destroy()
120 CaptureVoiceOut *cap; in wav_start_capture() local
173 cap = AUD_add_capture(state, &as, &ops, wav); in wav_start_capture()
174 if (!cap) { in wav_start_capture()
179 wav->cap = cap; in wav_start_capture()
/qemu/include/block/
H A Dnvme.h7 uint64_t cap; member
37 NVME_REG_CAP = offsetof(NvmeBar, cap),
109 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) argument
110 #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) argument
111 #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) argument
112 #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) argument
113 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) argument
114 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) argument
115 #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) argument
116 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) argument
[all …]
H A Dufs.h9 uint32_t cap; member
58 REG32(CAP, offsetof(UfsReg, cap))
59 FIELD(CAP, NUTRS, 0, 5)
60 FIELD(CAP, RTT, 8, 8)
61 FIELD(CAP, NUTMRS, 16, 3)
62 FIELD(CAP, AUTOH8, 23, 1)
63 FIELD(CAP, 64AS, 24, 1)
64 FIELD(CAP, OODDS, 25, 1)
65 FIELD(CAP, UICDMETMS, 26, 1)
66 FIELD(CAP, CS, 28, 1)
[all …]
/qemu/tests/qtest/
H A Dppc-util.h14 "cap-cfpc=broken," \
15 "cap-sbbc=broken," \
16 "cap-ibs=broken," \
17 "cap-ccf-assist=off,"
H A Dintel-iommu-test.c29 uint64_t cap, ecap, tmp; in test_intel_iommu_stage_1() local
34 cap = vtd_reg_readq(s, DMAR_CAP_REG); in test_intel_iommu_stage_1()
35 g_assert((cap & CAP_STAGE_1_FIXED1) == CAP_STAGE_1_FIXED1); in test_intel_iommu_stage_1()
37 tmp = cap & VTD_CAP_SAGAW_MASK; in test_intel_iommu_stage_1()
40 tmp = VTD_MGAW_FROM_CAP(cap); in test_intel_iommu_stage_1()
H A Dnvme-test.c76 uint64_t cap; in nvmetest_reg_read_test() local
87 cap = qpci_io_readq(pdev, bar, 0x0); in nvmetest_reg_read_test()
88 g_assert_cmpint(NVME_CAP_MQES(cap), ==, 0x7ff); in nvmetest_reg_read_test()
89 g_assert_cmpint(NVME_CAP_MPSMAX(cap), ==, 0x4); in nvmetest_reg_read_test()
H A Dahci-test.c99 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap); in verify_state()
342 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */ in ahci_test_pci_spec()
380 g_test_message("Unknown CAP 0x%02x", cid); in ahci_test_pci_caps()
488 * CAP.SSS - Support for staggered spin-up (t/f) in ahci_test_hba_spec()
489 * CAP.SMPS - Support for mechanical presence switches (t/f) in ahci_test_hba_spec()
495 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97: in ahci_test_hba_spec()
506 /* 1 CAP - Capabilities Register */ in ahci_test_hba_spec()
507 ahci->cap = ahci_rreg(ahci, AHCI_CAP); in ahci_test_hba_spec()
508 ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED); in ahci_test_hba_spec()
515 if (BITSET(ahci->cap, AHCI_CAP_SAM)) { in ahci_test_hba_spec()
[all …]
/qemu/tests/qtest/libqos/
H A Dpci.c107 uint8_t cap = 0; in qpci_find_resource_reserve_capability() local
121 cap = qpci_find_capability(dev, PCI_CAP_ID_VNDR, cap); in qpci_find_resource_reserve_capability()
122 } while (cap && in qpci_find_resource_reserve_capability()
123 qpci_config_readb(dev, cap + REDHAT_PCI_CAP_TYPE_OFFSET) != in qpci_find_resource_reserve_capability()
125 if (cap) { in qpci_find_resource_reserve_capability()
126 uint8_t cap_len = qpci_config_readb(dev, cap + PCI_CAP_FLAGS); in qpci_find_resource_reserve_capability()
131 return cap; in qpci_find_resource_reserve_capability()
184 uint8_t cap = qpci_find_resource_reserve_capability(dev); in qpci_secondary_buses_rec() local
186 if (cap) { in qpci_secondary_buses_rec()
189 tmp_res_bus = qpci_config_readl(dev, cap + in qpci_secondary_buses_rec()
[all …]
/qemu/include/system/
H A Dkvm.h172 #define KVM_CAP_INFO(CAP) { "KVM_CAP_" stringify(CAP), KVM_CAP_##CAP } argument
452 struct kvm_enable_cap cap = { \
453 .cap = capability, \
457 size_t n = MIN(ARRAY_SIZE(args_tmp), ARRAY_SIZE(cap.args)); \
458 memcpy(cap.args, args_tmp, n * sizeof(cap.args[0])); \
459 kvm_vm_ioctl(s, KVM_ENABLE_CAP, &cap); \
464 struct kvm_enable_cap cap = { \
465 .cap = capability, \
469 size_t n = MIN(ARRAY_SIZE(args_tmp), ARRAY_SIZE(cap.args)); \
470 memcpy(cap.args, args_tmp, n * sizeof(cap.args[0])); \
[all …]
H A Dhost_iommu_device.h88 * of @cap.
92 * @cap: capability to check.
96 * Returns: <0 on failure, 0 if a @cap is unsupported, or else
97 * 1 or some positive value for some special @cap,
100 int (*get_cap)(HostIOMMUDevice *hiod, int cap, Error **errp);
H A Dkvm_xen.h32 #define kvm_xen_has_cap(cap) (!!(kvm_xen_get_caps() & \ argument
33 KVM_XEN_HVM_CONFIG_ ## cap))
/qemu/hw/usb/
H A Ddesc.c273 d->u.cap.bDevCapabilityType = USB_DEV_CAP_USB2_EXT; in usb_desc_cap_usb2_ext()
275 d->u.cap.u.usb2_ext.bmAttributes_1 = (1 << 1); /* LPM */ in usb_desc_cap_usb2_ext()
276 d->u.cap.u.usb2_ext.bmAttributes_2 = 0; in usb_desc_cap_usb2_ext()
277 d->u.cap.u.usb2_ext.bmAttributes_3 = 0; in usb_desc_cap_usb2_ext()
278 d->u.cap.u.usb2_ext.bmAttributes_4 = 0; in usb_desc_cap_usb2_ext()
294 d->u.cap.bDevCapabilityType = USB_DEV_CAP_SUPERSPEED; in usb_desc_cap_super()
296 d->u.cap.u.super.bmAttributes = 0; in usb_desc_cap_super()
297 d->u.cap.u.super.wSpeedsSupported_lo = 0; in usb_desc_cap_super()
298 d->u.cap.u.super.wSpeedsSupported_hi = 0; in usb_desc_cap_super()
299 d->u.cap.u.super.bFunctionalitySupport = 0; in usb_desc_cap_super()
[all …]
/qemu/hw/virtio/
H A Dvirtio-pci.c783 off = le32_to_cpu(cfg->cap.offset); in virtio_write_config()
784 caplen = le32_to_cpu(cfg->cap.length); in virtio_write_config()
807 off = le32_to_cpu(cfg->cap.offset); in virtio_read_config()
808 caplen = le32_to_cpu(cfg->cap.length); in virtio_read_config()
1414 struct virtio_pci_cap *cap) in virtio_pci_add_mem_cap() argument
1420 cap->cap_len, &error_abort); in virtio_pci_add_mem_cap()
1422 assert(cap->cap_len >= sizeof *cap); in virtio_pci_add_mem_cap()
1423 memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len, in virtio_pci_add_mem_cap()
1424 cap->cap_len - PCI_CAP_FLAGS); in virtio_pci_add_mem_cap()
1465 struct virtio_pci_cap64 cap = { in virtio_pci_add_shm_cap() local
[all …]
/qemu/tests/functional/
H A Dtest_ppc64_hv.py111 '-machine cap-cfpc=broken,cap-sbbc=broken,'
112 'cap-ibs=broken,cap-ccf-assist=off '
132 self.vm.add_args("-machine", "x-vof=on,cap-nested-hv=on")
144 self.vm.add_args("-machine", "x-vof=on,cap-nested-hv=on,cap-ccf-assist=off")
/qemu/hw/ufs/
H A Dufs.c98 if (!FIELD_EX32(u->reg.cap, CAP, 64AS) && (hi >> 32)) { in ufs_addr_read()
113 if (!FIELD_EX32(u->reg.cap, CAP, 64AS) && (hi >> 32)) { in ufs_addr_write()
1686 uint32_t cap = 0; in ufs_init_hc() local
1695 cap = FIELD_DP32(cap, CAP, NUTRS, (u->params.nutrs - 1)); in ufs_init_hc()
1696 cap = FIELD_DP32(cap, CAP, RTT, 2); in ufs_init_hc()
1697 cap = FIELD_DP32(cap, CAP, NUTMRS, (u->params.nutmrs - 1)); in ufs_init_hc()
1698 cap = FIELD_DP32(cap, CAP, AUTOH8, 0); in ufs_init_hc()
1699 cap = FIELD_DP32(cap, CAP, 64AS, 1); in ufs_init_hc()
1700 cap = FIELD_DP32(cap, CAP, OODDS, 0); in ufs_init_hc()
1701 cap = FIELD_DP32(cap, CAP, UICDMETMS, 0); in ufs_init_hc()
[all …]
/qemu/target/arm/
H A Darm-qmp-cmds.c37 GICCapability *cap = g_new0(GICCapability, 1); in gic_cap_new() local
38 cap->version = version; in gic_cap_new()
40 cap->emulated = false; in gic_cap_new()
41 cap->kernel = false; in gic_cap_new()
42 return cap; in gic_cap_new()
/qemu/hw/riscv/
H A Driscv-iommu.c320 if (!(s->cap & sv_mode)) { in riscv_iommu_spa_fetch()
340 if (!(s->cap & sv_mode)) { in riscv_iommu_spa_fetch()
349 if (!(s->cap & sv_mode)) { in riscv_iommu_spa_fetch()
358 if (!(s->cap & sv_mode)) { in riscv_iommu_spa_fetch()
710 if (!(s->cap & RISCV_IOMMU_CAP_ATS) && in riscv_iommu_validate_device_ctx()
728 if (!(s->cap & RISCV_IOMMU_CAP_T2GPA) && in riscv_iommu_validate_device_ctx()
733 if (s->cap & RISCV_IOMMU_CAP_MSI_FLAT) { in riscv_iommu_validate_device_ctx()
753 if (!(s->cap & RISCV_IOMMU_CAP_PD8)) { in riscv_iommu_validate_device_ctx()
758 if (!(s->cap & RISCV_IOMMU_CAP_PD17)) { in riscv_iommu_validate_device_ctx()
763 if (!(s->cap & RISCV_IOMMU_CAP_PD20)) { in riscv_iommu_validate_device_ctx()
[all …]
/qemu/include/hw/cxl/
H A Dcxl_pci.h16 #define PCIE_DVSEC_HEADER1_OFFSET 0x4 /* Offset from start of extend cap */
79 uint16_t cap; member
154 uint16_t cap; member

123456