Home
last modified time | relevance | path

Searched +full:cache +full:- +full:unified (Results 1 – 25 of 182) sorted by relevance

12345678

/linux-5.10/tools/perf/pmu-events/arch/arm64/
Darmv8-recommended.json3 "PublicDescription": "Attributable Level 1 data cache access, read",
6 "BriefDescription": "L1D cache access, read"
9 "PublicDescription": "Attributable Level 1 data cache access, write",
12 "BriefDescription": "L1D cache access, write"
15 "PublicDescription": "Attributable Level 1 data cache refill, read",
18 "BriefDescription": "L1D cache refill, read"
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
24 "BriefDescription": "L1D cache refill, write"
27 "PublicDescription": "Attributable Level 1 data cache refill, inner",
30 "BriefDescription": "L1D cache refill, inner"
[all …]
/linux-5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/
Dcache.json3 …"PublicDescription": "L1 instruction cache refill. This event counts any instruction fetch which m…
6 "BriefDescription": "L1 instruction cache refill"
15 …"PublicDescription": "L1 data cache refill. This event counts any load or store operation or page …
18 "BriefDescription": "L1 data cache refill"
21 …tion": "L1 data cache access. This event counts any load or store operation or page table walk acc…
24 "BriefDescription": "L1 data cache access"
33 …on cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which ac…
36 "BriefDescription": "L1 instruction cache access"
39 …cache Write-Back. This event counts any write-back of data from the L1 data cache to L2 or L3. Thi…
42 "BriefDescription": "L1 data cache Write-Back"
[all …]
/linux-5.10/Documentation/devicetree/bindings/arm/socionext/
Dsocionext,uniphier-system-cache.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
[all …]
/linux-5.10/Documentation/devicetree/bindings/nds32/
Datl2c.txt1 * Andestech L2 cache Controller
3 The level-2 cache controller plays an important role in reducing memory latency
5 Level-2 cache controller in general enhances overall system performance
10 representation of an Andestech L2 cache controller.
13 - compatible:
17 - reg : Physical base address and size of cache controller's memory mapped
18 - cache-unified : Specifies the cache is a unified cache.
19 - cache-level : Should be set to 2 for a level 2 cache.
23 cache-controller@e0500000 {
26 cache-unified;
[all …]
/linux-5.10/Documentation/devicetree/bindings/riscv/
Dsifive-l2-cache.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive L2 Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Yash Shah <yash.shah@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
16 The SiFive Level 2 Cache Controller is used to provide access to fast copies
17 of memory for masters in a Core Complex. The Level 2 Cache Controller also
[all …]
/linux-5.10/arch/m68k/include/asm/
Dm53xxacr.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m53xxacr.h -- ColdFire version 3 core cache support
17 * cache setup. They have a unified instruction and data cache, with
18 * configurable write-through or copy-back operation.
22 * Define the Cache Control register flags.
24 #define CACR_EC 0x80000000 /* Enable cache */
27 #define CACR_HLCK 0x08000000 /* Half cache lock mode */
28 #define CACR_CINVA 0x01000000 /* Invalidate cache */
30 #define CACR_DCM_WT 0x00000000 /* Cacheable write-through */
31 #define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */
[all …]
/linux-5.10/arch/arm/mm/
Dcache-v6.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v6.S
15 #include "proc-macros.S"
25 * Flush the whole I-cache.
27 * ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
32 * r0 - set to 0
33 * r1 - corrupted
40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
41 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
[all …]
Dcache-uniphier.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015-2016 Socionext Inc.
15 #include <asm/hardware/cache-uniphier.h>
21 #define UNIPHIER_SSCC_ACT BIT(19) /* Inst-Data separate */
23 #define UNIPHIER_SSCC_PRD BIT(17) /* enable pre-fetch */
24 #define UNIPHIER_SSCC_ON BIT(0) /* enable cache */
25 #define UNIPHIER_SSCLPDAWCR 0x30 /* Unified/Data Active Way Control */
32 #define UNIPHIER_SSCOPE 0x244 /* Cache Operation Primitive Entry */
37 #define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
38 #define UNIPHIER_SSCOQM 0x248 /* Cache Operation Queue Mode */
[all …]
Dcopypage-v4wt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mm/copypage-v4wt.S
5 * Copyright (C) 1995-1999 Russell King
7 * This is for CPUs with a writethrough cache and 'flush ID cache' is
8 * the only supported cache operation.
17 * dirty data in the cache. However, we do have to ensure that
25 .syntax unified\n\ in v4wt_copy_user_page()
37 mcr p15, 0, %2, c7, c7, 0 @ flush ID cache" in v4wt_copy_user_page()
75 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache" in v4wt_clear_user_highpage()
/linux-5.10/Documentation/devicetree/bindings/arm/
Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
14 PL220/PL310 and variants) based level 2 cache controller. All these various
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
[all …]
/linux-5.10/arch/powerpc/kernel/
Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Processor cache information made available to userspace via sysfs;
27 /* per-cpu object for tracking:
28 * - a "cache" kobject for the top-level directory
29 * - a list of "index" objects representing the cpu's local cache hierarchy
32 struct kobject *kobj; /* bare (not embedded) kobject for cache
37 /* "index" object: each cpu's cache directory has an index
38 * subdirectory corresponding to a cache object associated with the
44 struct cache *cache; member
48 * cache type */
[all …]
/linux-5.10/arch/arm/boot/dts/
Dvf610.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 next-level-cache = <&L2>;
13 L2: cache-controller@40006000 {
14 compatible = "arm,pl310-cache";
16 cache-unified;
17 cache-level = <2>;
18 arm,data-latency = <3 3 3>;
19 arm,tag-latency = <2 2 2>;
Dhighbank.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
25 next-level-cache = <&L2>;
27 clock-names = "cpu";
[all …]
Dzx296702.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/zx296702-clock.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
13 enable-method = "zte,zx296702-smp";
16 compatible = "arm,cortex-a9";
18 next-level-cache = <&l2cc>;
[all …]
/linux-5.10/drivers/acpi/
Dpptt.c1 // SPDX-License-Identifier: GPL-2.0
3 * pptt.c - parsing of Processor Properties Topology Table (PPTT)
8 * which is optionally used to describe the processor and cache topology.
14 * the caches available at that level. Each cache structure optionally
15 * contains properties describing the cache at a given level which can be
33 if (pptt_ref + sizeof(struct acpi_subtable_header) > table_hdr->length) in fetch_pptt_subtable()
38 if (entry->length == 0) in fetch_pptt_subtable()
41 if (pptt_ref + entry->length > table_hdr->length) in fetch_pptt_subtable()
65 if (resource >= node->number_of_priv_resources) in acpi_get_pptt_resource()
81 * acpi_pptt_walk_cache() - Attempt to find the requested acpi_pptt_cache
[all …]
/linux-5.10/arch/sh/kernel/cpu/
Dproc.c1 // SPDX-License-Identifier: GPL-2.0
21 [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
26 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
27 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
36 return cpu_name[c->type]; in get_cpu_subtype()
41 /* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
53 if (!c->flags) { in show_cpuflags()
59 if ((c->flags & (1 << i))) in show_cpuflags()
72 seq_printf(m, "%s size\t: %2dKiB (%d-way)\n", in show_cacheinfo()
82 unsigned int cpu = c - cpu_data; in show_cpuinfo()
[all …]
/linux-5.10/arch/nds32/boot/dts/
Dae3xx.dts1 /dts-v1/;
4 #address-cells = <1>;
5 #size-cells = <1>;
6 interrupt-parent = <&intc>;
9 stdout-path = &serial0;
18 #address-cells = <1>;
19 #size-cells = <0>;
24 clock-frequency = <60000000>;
25 next-level-cache = <&L2>;
29 intc: interrupt-controller {
[all …]
/linux-5.10/fs/nilfs2/
Dalloc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * alloc.h - persistent object (dat entry/disk inode) allocator/deallocator
5 * Copyright (C) 2006-2008 Nippon Telegraph and Telephone Corporation.
8 * Two allocators were unified by Ryusuke Konishi and Amagai Yoshiji.
19 * nilfs_palloc_entries_per_group - get the number of entries per group
28 return 1UL << (inode->i_blkbits + 3 /* log2(8 = CHAR_BITS) */); in nilfs_palloc_entries_per_group()
40 * nilfs_palloc_req - persistent allocator request and reply
69 * struct nilfs_bh_assoc - block offset and buffer head association
79 * struct nilfs_palloc_cache - persistent object allocator cache
80 * @lock: cache protecting lock
[all …]
/linux-5.10/arch/arm/kernel/
Dhead-nommu.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-nommu.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2006 Hyok S. Choi
8 * Common kernel startup code (non-paged MM)
16 #include <asm/asm-offsets.h>
26 * ---------------------------
29 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
32 * See linux/arch/arm/tools/mach-types for the complete list of machine
47 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
[all …]
/linux-5.10/drivers/base/
Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0
3 * cacheinfo support - processor cache information via sysfs
26 #define cache_leaves(cpu) (ci_cacheinfo(cpu)->num_leaves)
27 #define per_cpu_cacheinfo(cpu) (ci_cacheinfo(cpu)->info_list)
38 return sib_leaf->fw_token == this_leaf->fw_token; in cache_leaves_are_shared()
41 /* OF properties to query for a given cache type */
50 .size_prop = "cache-size",
51 .line_size_props = { "cache-line-size",
52 "cache-block-size", },
53 .nr_sets_prop = "cache-sets",
[all …]
/linux-5.10/Documentation/devicetree/bindings/power/
Drenesas,rcar-sysc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/power/renesas,rcar-sysc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Renesas R-Car and RZ/G System Controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The R-Car (RZ/G) System Controller provides power management for the CPU
20 - renesas,r8a7742-sysc # RZ/G1H
21 - renesas,r8a7743-sysc # RZ/G1M
[all …]
/linux-5.10/include/linux/
Dcacheinfo.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 * struct cacheinfo - represent a cache leaf node
25 * @id: This cache's id. It is unique among caches with the same (type, level).
26 * @type: type of the cache - data, inst or unified
27 * @level: represents the hierarchy in the multi-level cache
28 * @coherency_line_size: size of each cache line usually representing
30 * @number_of_sets: total number of sets, a set is a collection of cache
33 * block can be placed in the cache
34 * @physical_line_partition: number of physical cache lines sharing the
36 * @size: Total size of the cache
[all …]
/linux-5.10/arch/ia64/kernel/
Dtopology.c10 * Populate cpu entries in sysfs for non-numa systems as well
11 * Intel Corporation - Ashok Raj
13 * Populate cpu cache entries in sysfs for cpu cache info
35 if (cpu_data(num)->socket_id == -1) in arch_fix_phys_package_id()
36 cpu_data(num)->socket_id = slot; in arch_fix_phys_package_id()
46 * If CPEI can be re-targeted or if this is not in arch_register_cpu()
76 * MCD - Do we want to register all ONLINE nodes, or all POSSIBLE nodes? in topology_init()
86 panic("kzalloc in topology_init failed - NR_CPUS too big?"); in topology_init()
100 * Export cpu cache information through sysfs
110 "Unified" /* unified */
[all …]
/linux-5.10/arch/s390/kernel/
Dcache.c1 // SPDX-License-Identifier: GPL-2.0
3 * Extract CPU cache information and expose them via sysfs.
58 "Unified",
71 struct cacheinfo *cache; in show_cacheinfo() local
77 for (idx = 0; idx < this_cpu_ci->num_leaves; idx++) { in show_cacheinfo()
78 cache = this_cpu_ci->info_list + idx; in show_cacheinfo()
79 seq_printf(m, "cache%-11d: ", idx); in show_cacheinfo()
80 seq_printf(m, "level=%d ", cache->level); in show_cacheinfo()
81 seq_printf(m, "type=%s ", cache_type_string[cache->type]); in show_cacheinfo()
83 cache->disable_sysfs ? "Shared" : "Private"); in show_cacheinfo()
[all …]
/linux-5.10/drivers/gpu/drm/amd/amdkfd/
Dkfd_flat_memory.c56 * System Unified Address - SUA
69 * system unified address (SUA).
80 * HSA64 - ATC/IOMMU 64b
90 * unified address” feature (SUA) is the mapping of GPUVM and ATC address
91 * spaces into a unified pointer space. The method we take for 64b mode is
133 * requests to the cache/memory system. This is the case for the
137 * In all cases (no matter where the 64b -> 49b conversion is done), the gfxip
152 * config tables for setting cache policies. The “spare” (APE1) aperture is
188 * HSA32 - ATC/IOMMU 32b
205 * Device Unified Address - DUA
[all …]

12345678