boot/dts/ae3xx.dts

1 /dts-v1/;
4 	#address-cells = <1>;
5 	#size-cells = <1>;
6 	interrupt-parent = <&intc>;
9 		stdout-path = &serial0;
18 		#address-cells = <1>;
19 		#size-cells = <0>;
24 			clock-frequency = <60000000>;
25 			next-level-cache = <&L2>;
29 	intc: interrupt-controller {
31 		#interrupt-cells = <1>;
32 		interrupt-controller;
36 		#clock-cells = <0>;
37 		compatible = "fixed-clock";
38 		clock-frequency = <30000000>;
42 		compatible = "simple-bus";
43 		#address-cells = <1>;
44 		#size-cells = <1>;
51 			clock-frequency = <14745600>;
52 			reg-shift = <2>;
53 			reg-offset = <32>;
54 			no-loopback-test = <1>;
62 			clock-names = "PCLK";
67 		compatible = "simple-bus";
68 		#address-cells = <1>;
69 		#size-cells = <1>;
72 		L2: cache-controller@e0500000 {
75 			cache-unified;
76 			cache-level = <2>;
87 		compatible = "andestech,nds32v3-pmu";