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/linux-6.8/arch/arm64/boot/dts/realtek/
Drtd16xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
[all …]
Drtd129x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2016-2019 Andreas Färber
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/realtek,rtd1295.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
Drtd139x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/realtek,rtd1295.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
34 no-map;
[all …]
/linux-6.8/arch/arm64/boot/dts/intel/
Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
[all …]
/linux-6.8/arch/arm64/boot/dts/amazon/
Dalpine-v2.dtsi4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
[all …]
Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
[all …]
/linux-6.8/arch/arm/boot/dts/realtek/
Drtd1195.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 * Copyright (c) 2017-2019 Andreas Färber
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/realtek,rtd1195.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a7";
[all …]
/linux-6.8/drivers/iommu/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += amd/ intel/ arm/ iommufd/
3 obj-$(CONFIG_IOMMU_API) += iommu.o
4 obj-$(CONFIG_IOMMU_API) += iommu-traces.o
5 obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o
6 obj-$(CONFIG_IOMMU_DEBUGFS) += iommu-debugfs.o
7 obj-$(CONFIG_IOMMU_DMA) += dma-iommu.o
8 obj-$(CONFIG_IOMMU_IO_PGTABLE) += io-pgtable.o
9 obj-$(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) += io-pgtable-arm-v7s.o
10 obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o
[all …]
/linux-6.8/Documentation/devicetree/bindings/serial/
Dpl011.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM AMBA Primecell PL011 serial UART
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/arm/primecell.yaml#
14 - $ref: serial.yaml#
16 # Need a custom select here or 'arm,primecell' will match on lots of nodes
22 - arm,pl011
24 - compatible
[all …]
/linux-6.8/Documentation/devicetree/bindings/arm/
Dapple.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/apple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple ARM Machine
10 - Hector Martin <marcan@marcan.st>
13 ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon".
17 - Mac mini (M1, 2020)
18 - MacBook Pro (13-inch, M1, 2020)
19 - MacBook Air (M1, 2020)
[all …]
/linux-6.8/arch/arm/boot/dts/rockchip/
Drk3xxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
37 compatible = "fixed-clock";
38 clock-frequency = <24000000>;
39 #clock-cells = <0>;
[all …]
Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
[all …]
/linux-6.8/arch/arm64/boot/dts/bitmain/
Dbm1880.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/bm1880-clock.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
[all …]
/linux-6.8/arch/arm/boot/dts/marvell/
Darmada-39x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "marvell,armada-390-smp";
37 compatible = "arm,cortex-a9";
[all …]
/linux-6.8/arch/arm/mm/
Dpmsa-v8.c2 * Based on linux/arch/arm/pmsa-v7.c
4 * ARM PMSAv8 supporting functions.
78 static struct range __initdata io[MPU_MAX_REGIONS]; variable
120 memblock_remove(reg_start, 0 - reg_start); in pmsav8_adjust_lowmem_bounds()
145 return -ENOENT; in __pmsav8_setup_region()
166 return -EINVAL; in pmsav8_setup_ram()
169 lar = (end - 1) & ~(PMSAv8_MINALIGN - 1); in pmsav8_setup_ram()
182 return -EINVAL; in pmsav8_setup_io()
185 lar = (end - 1) & ~(PMSAv8_MINALIGN - 1); in pmsav8_setup_io()
198 return -EINVAL; in pmsav8_setup_fixed()
[all …]
/linux-6.8/arch/arm/boot/dts/renesas/
Dr9a06g032.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
33 enable-method = "renesas,r9a06g032-smp";
[all …]
/linux-6.8/arch/arm64/boot/dts/allwinner/
Dsun50i-a100.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
8 #include <dt-bindings/clock/sun50i-a100-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-a100-ccu.h>
10 #include <dt-bindings/reset/sun50i-a100-r-ccu.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
[all …]
/linux-6.8/arch/arm/boot/dts/amazon/
Dalpine.dtsi27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-smp";
47 compatible = "arm,cortex-a15";
50 clock-frequency = <1700000000>;
54 compatible = "arm,cortex-a15";
57 clock-frequency = <1700000000>;
[all …]
/linux-6.8/arch/arm64/kernel/
Dio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/io.c
5 * Copyright (C) 2012 ARM Ltd.
10 #include <linux/io.h>
13 * Copy data from IO memory space to "real" memory space.
21 count--; in __memcpy_fromio()
28 count -= 8; in __memcpy_fromio()
35 count--; in __memcpy_fromio()
41 * Copy data from "real" memory space to IO memory space.
49 count--; in __memcpy_toio()
[all …]
/linux-6.8/arch/arm64/boot/dts/marvell/
Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
[all …]
Dac5-98dx25xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <2>;
21 #size-cells = <0>;
23 cpu-map {
36 compatible = "arm,cortex-a55";
[all …]
/linux-6.8/arch/arm/boot/dts/broadcom/
Dbcm-cygnus.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-cygnus.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
[all …]
/linux-6.8/arch/arm/include/asm/
Dio.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/include/asm/io.h
5 * Copyright (C) 1996-2000 Russell King
8 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
10 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
11 * specific IO header files.
12 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
13 * 04-Apr-1999 PJB Added check_signature.
14 * 12-Dec-1999 RMK More cleanups
15 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
[all …]
/linux-6.8/arch/arm64/boot/dts/broadcom/northstar2/
Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
[all …]
/linux-6.8/arch/arm64/boot/dts/arm/
Dcorstone1000-fvp.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (c) 2022, Arm Limited. All rights reserved.
8 /dts-v1/;
13 model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
14 compatible = "arm,corstone1000-fvp";
19 phy-mode = "mii";
21 reg-io-width = <2>;
25 compatible = "regulator-fixed";
26 regulator-name = "vmmc_supply";
27 regulator-min-microvolt = <3300000>;
[all …]

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