include/asm/io.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  arch/arm/include/asm/io.h
5  *  Copyright (C) 1996-2000 Russell King
8  *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
10  *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
11  *			specific IO header files.
12  *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
13  *  04-Apr-1999	PJB	Added check_signature.
14  *  12-Dec-1999	RMK	More cleanups
15  *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
16  *  05-Oct-2004 BJD     Moved memory string functions to use void __iomem
27 #include <asm-generic/pci_iomap.h>
36  * Atomic MMIO-wide IO modify
42  * Generic IO read/write.  These perform native-endian accesses.  Note
43  * that some architectures will want to re-define __raw_{read,write}w.
55  * Half-word accesses are problematic with RiscPC due to limitations of
56  * the bus. Rather than special-case the machine, just let the compiler
135  * /proc/vmalloc to use - and should only be used in non-inline functions.
161 /* IO barriers */
197  * Now, pick up the machine-defined IO definitions
200 #include <mach/io.h>
211  *  IO port access primitives
212  *  -------------------------
214  * The ARM doesn't have special IO access instructions; all IO is memory
220  * ARM documents:
222  *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
223  *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
225  * The machine specific io.h include defines __io to translate an "IO"
228  * Note that we prevent GCC re-ordering or caching values in expressions
232  * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
257  * String version of IO memory access ops:
265  *  ------------------------
271  * IO port primitives for more information.
336  * ioremap() takes a resource address, and size.  Due to the ARM memory
343  * ioremap_wc()		Normal		Non-cacheable	n/a
344  * ioremap_wt()		Normal		Non-cacheable	n/a
347  * - no access speculation
348  * - no repetition (eg, on return from an exception)
349  * - number, order and size of accesses are maintained
350  * - unaligned accesses are "unpredictable"
351  * - writes may be delayed before they hit the endpoint device
354  * - reads can be repeated with no side effects
355  * - repeated reads return the last value written
356  * - reads can fetch additional locations without side effects
357  * - writes can be repeated (in certain cases) with no side effects
358  * - writes can be merged before accessing the target
359  * - unaligned accesses can be supported
360  * - ordering is not guaranteed without explicit dependencies or barrier
362  * - writes may be delayed before they hit the endpoint memory
388  * io{read,write}{16,32}be() macros
410 #include <asm-generic/io.h>
425 extern void register_isa_ports(unsigned int mmio, unsigned int io,