| /qemu/docs/system/openrisc/ |
| H A D | emulation.rst | 1 OpenRISC 1000 CPU architecture support
5 the OpenRISC 1000 cpu architecture.
16 architecture manual available on the OpenRISC website in the
17 `OpenRISC Architecture <https://openrisc.io/architecture>`_ section.
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| /qemu/scripts/ci/setup/ubuntu/ |
| H A D | build-environment.yml | 22 - name: Add armhf foreign architecture to aarch64 hosts
23 command: dpkg --add-architecture armhf
26 - ansible_facts['architecture'] == 'aarch64'
36 - name: Include package lists based on OS and architecture
38 file: "ubuntu-2204-{{ ansible_facts['architecture'] }}.yaml"
66 - ansible_facts['architecture'] == 'aarch64'
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| /qemu/scripts/ci/setup/ |
| H A D | gitlab-runner.yml | 46 - name: Set the architecture for gitlab-runner
48 gitlab_runner_arch: "{{ ansible_to_gitlab_arch[ansible_facts[\"architecture\"]] }}"
98 …architecture\"] }},{{ ansible_facts[\"distribution\"]|lower }}_{{ ansible_facts[\"distribution_ver…
102 …] }} {{ ansible_facts[\"distribution_version\"] }} {{ ansible_facts[\"architecture\"] }} ({{ ansib…
105 - ansible_facts['architecture'] == 'aarch64'
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| /qemu/docs/system/arm/ |
| H A D | emulation.rst | 3 A-profile CPU architecture support
7 Armv8 and Armv9 versions of the A-profile architecture. It also has support for
8 the following architecture extensions:
162 to the `Arm Architecture Reference Manual for A-profile architecture
170 R-profile CPU architecture support
176 M-profile CPU architecture support
181 for the following architecture extensions:
195 to the `Armv8-M Arm Architecture Reference Manual
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| H A D | sbsa.rst | 1 Arm Server Base System Architecture Reference board (``sbsa-ref``)
9 - `Base System Architecture <https://developer.arm.com/documentation/den0094/>`__ (BSA)
10 - `Server Base System Architecture <https://developer.arm.com/documentation/den0029/>`__ (SBSA)
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| /qemu/docs/interop/ |
| H A D | firmware.json | 56 # is specific to the target architecture and machine type.
91 # @architecture: Determines the emulation target (the QEMU system
95 # specified through @architecture) that can execute the
107 'data' : { 'architecture' : 'FirmwareArchitecture',
136 # Virtualization, as specified in the AMD64 Architecture
143 # Architecture Programmer's Manual. QEMU command line options
149 # AMD64 Architecture Programmer's Manual. QEMU command line
163 # Architecture Programmer's Manual, and in the Intel(R)64
496 # "architecture": "i386",
503 # "architecture": "x86_64",
[all …]
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| /qemu/target/mips/ |
| H A D | msa.c | 2 * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
53 * (per "MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD in msa_reset()
54 * Architecture Module, Revision 1.1" section 3.5.4), even though it in msa_reset()
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| /qemu/docs/ |
| H A D | glossary.rst | 82 Guest is the architecture of the virtual machine, which is emulated.
85 Sometimes this is called the :ref:`target` architecture, but that term
93 Host is the architecture on which QEMU is running on, which is native.
180 architecture agnostic instrumentation.
249 architecture which QEMU is running on, i.e. the :ref:`host`.
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| /qemu/docs/devel/ |
| H A D | codebase.rst | 49 Infrastructure and architecture agnostic code related to the various
94 Various architecture specific header files (crypto, atomic, memory
101 architecture.
109 type/protocol/architecture and located in associated subfolder.
170 per arch). For every architecture, you can find accelerator specific
174 Contains one subfolder per host supported architecture.
201 `TCG related tests <checktcg-ref>`. Contains code per architecture
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| H A D | tcg-ops.rst | 17 The TCG *target* is the architecture for which we generate the code.
19 emulated architecture. As TCG started as a generic C backend used
23 In this document, we use *guest* to specify what architecture we are
599 carry bit provided by the host architecture.
604 input carry bit provided by the host architecture.
610 input carry bit provided by the host architecture,
616 carry bit provided by the host architecture. This is akin to
628 borrow bit provided by the host architecture.
629 | Depending on the host architecture, the carry bit may or may not be
636 input borrow bit provided by the host architecture.
[all …]
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| /qemu/docs/system/riscv/ |
| H A D | microblaze-v-generic.rst | 5 64-bit) RISC-V instruction set architecture (ISA) and contains interfaces
10 https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/MicroBlaze-V-Architecture
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| /qemu/docs/system/ |
| H A D | target-sparc.rst | 7 architecture machines:
54 The number of peripherals is fixed in the architecture. Maximum memory
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| H A D | target-openrisc.rst | 9 on FPGAs. These SoCs are based on the same core architecture as the or1ksim
61 Emulated CPU architecture support
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| /qemu/target/hexagon/ |
| H A D | attribs_def.h.inc | 31 DEF_ATTRIB(ARCHV2, "V2 architecture", "", "")
32 DEF_ATTRIB(ARCHV3, "V3 architecture", "", "")
33 DEF_ATTRIB(ARCHV4, "V4 architecture", "", "")
34 DEF_ATTRIB(ARCHV5, "V5 architecture", "", "")
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| /qemu/python/qemu/utils/ |
| H A D | accel.py | 25 # Mapping host architecture to any additional architectures it can
62 @param target_arch (str): target architecture
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| /qemu/target/alpha/ |
| H A D | machine.c | 30 /* Save the architecture value of the fpcr, not the internally
31 expanded version. Since this architecture value does not
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| /qemu/.gitlab/issue_templates/ |
| H A D | bug.md | 23 - Architecture: <!-- x86, ARM, s390x, etc. -->
40 - Architecture: <!-- x86, ARM, s390x, etc. -->
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| /qemu/tests/functional/ |
| H A D | test_microblaze_s3adsp1800.py | 37 wait_for_console_pattern(self, 'This architecture does not have '
40 # The kernel sometimes gets stuck after the "This architecture ..."
|
| /qemu/scripts/ |
| H A D | probe-gdb-support.py | 8 # passed a GDB binary will probe its architecture support and return a
58 "-ex", "set architecture",
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| /qemu/docs/about/ |
| H A D | emulation.rst | 7 depending on the guest architecture.
13 * - Architecture (qemu name)
40 - The ubiquitous desktop PC CPU architecture, 32 and 64 bit.
44 - A MIPS-like 64bit RISC architecture developed in China
56 - Venerable RISC architecture originally out of Stanford University
60 - Open source RISC architecture developed by the OpenRISC community
64 - A general purpose RISC architecture now managed by IBM
99 Semihosting is a feature defined by the owner of the architecture to
145 for that architecture.
160 * - Architecture
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| H A D | build-platforms.rst | 43 * - CPU Architecture
61 emulation on an unsupported host architecture using the configure
122 with one exception, namely the ``mips64el`` architecture on Debian bookworm.
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| /qemu/include/hw/ppc/ |
| H A D | spapr_ovec.h | 2 * QEMU SPAPR Option/Architecture Vector Definitions
4 * Each architecture option is organized/documented by the following
|
| /qemu/docs/specs/ |
| H A D | ppc-spapr-hcalls.rst | 7 Architecture Reference ([LoPAR]_) document. This document is a subset of the
8 Power Architecture Platform Reference (PAPR+) specification (IBM internal only),
|
| /qemu/tests/docker/dockerfiles/ |
| H A D | debian-riscv64-cross.docker | 46 dpkg --add-architecture riscv64 && \
74 dpkg-query --showformat '${Package}_${Version}_${Architecture}\n' --show > /packages.txt && \
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| /qemu/target/mips/tcg/ |
| H A D | rel6.decode | 9 # MIPS Architecture for Programmers Volume II-A
13 # MIPS Architecture for Programmers Volume II-A
|