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/qemu/hw/ppc/
H A Dppc440_uc.c435 /* PLB to AHB bridge */
448 ppc4xx_ahb_t *ahb = opaque; in dcr_read_ahb() local
453 ret = ahb->top; in dcr_read_ahb()
456 ret = ahb->bot; in dcr_read_ahb()
467 ppc4xx_ahb_t *ahb = opaque; in dcr_write_ahb() local
471 ahb->top = val; in dcr_write_ahb()
474 ahb->bot = val; in dcr_write_ahb()
481 ppc4xx_ahb_t *ahb = opaque; in ppc4xx_ahb_reset() local
484 ahb->top = 0; in ppc4xx_ahb_reset()
485 ahb->bot = 0; in ppc4xx_ahb_reset()
[all …]
H A Dpnv_pnor.c68 * TODO: Check endianness: skiboot is BIG, Aspeed AHB is LITTLE, flash
H A Dsam460ex.c364 /* PLB to AHB bridge */ in sam460ex_init()
/qemu/include/hw/misc/
H A Daspeed_scu.h108 * 18:16 MAC AHB bus clock divider selection
113 * 7 ARM CPU/AHB clock slow down enable
114 * 6:4 ARM CPU/AHB clock slow down setting
116 * 1 CPU/AHB clock slow down idle timer
117 * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4])
175 * 11:10 CPU/AHB clock frequency ratio selection
284 * 11:9 AXI/AHB clock frequency ratio selection
363 * 26:24 MAC AHB clock divider selection
H A Dgrlib_ahb_apb_pnp.h2 * GRLIB AHB APB PNP
H A Diotkit-secctl.h36 * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
H A Dtz-ppc.h28 * since the only difference between them is that the AHB version has a
/qemu/include/hw/arm/
H A Darmsse.h66 * + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows
69 * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit
76 * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
/qemu/hw/misc/
H A Dgrlib_ahb_apb_pnp.c2 * GRLIB AHB APB PNP
72 * AHB entries look like this: in grlib_ahb_pnp_add_entry()
119 /* AHB Memory Space */ in grlib_ahb_pnp_add_entry()
H A Dimx25_ccm.c205 * CPU = 133 MHz, AHB = 66,5 MHz, IPG = 33 MHz. in imx25_ccm_reset()
222 * CPU = 399 MHz, AHB = 133 MHz, IPG = 66,5 MHz. in imx25_ccm_reset()
H A Dallwinner-a10-ccm.c48 REG_CPU_AHB_APB0_CFG = 0x0054, /* CPU, AHB and APB0 Divide Ratio */
H A Diotkit-secctl.c113 /* The register sets for the various PPCs (AHB internal, APB internal,
114 * AHB expansion, APB expansion) are all set up so that they are
H A Dtrace-events347 grlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" s…
/qemu/tests/qtest/
H A Dstm32l4x5.h20 * AHB, APB1 and APB2 prescalers are set to 1 at reset.
H A Daspeed-smc-utils.c181 /* move out USER mode to use direct reads from the AHB bus */ in read_page_mem()
429 /* move out USER mode to use direct writes to the AHB bus */ in aspeed_smc_test_write_page_mem()
H A Dnpcm7xx_emc-test.c312 * During reset the AHB reads 0 for all registers. So first wait for in emc_soft_reset()
/qemu/hw/net/
H A Dmsf2-emac.c525 error_setg(errp, "MSS_EMAC 'ahb-bus' link not set"); in msf2_emac_realize()
529 address_space_init(&s->dma_as, s->dma_mr, "emac-ahb"); in msf2_emac_realize()
550 DEFINE_PROP_LINK("ahb-bus", MSF2EmacState, dma_mr,
/qemu/hw/arm/
H A Dmps2-tz.c650 * the MSC connects to the IoTKit AHB Slave Expansion port, so the in make_dma()
1096 { /* port 4 USER AHB interface 0 */ }, in mps2tz_common_init()
1097 { /* port 5 USER AHB interface 1 */ }, in mps2tz_common_init()
1098 { /* port 6 USER AHB interface 2 */ }, in mps2tz_common_init()
1099 { /* port 7 USER AHB interface 3 */ }, in mps2tz_common_init()
H A Dmps2.c260 create_unimplemented_device("CMSDK AHB peripheral region @0x40010000", in mps2_common_init()
364 create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000); in mps2_common_init()
H A Dmsf2-soc.c202 object_property_set_link(OBJECT(&s->emac), "ahb-bus", in m2sxxx_soc_realize()
H A Dversatilepb.c376 /* 0x101d0000 AHB Monitor Interface. */ in versatile_init()
H A Daspeed_ast2600.c28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
/qemu/hw/ssi/
H A Dxlnx-versal-ospi.c1674 qemu_log_mask(LOG_GUEST_ERROR, "OSPI AHB rd while DAC disabled\n"); in ospi_dac_read()
1677 qemu_log_mask(LOG_GUEST_ERROR, "OSPI AHB rd while OSPI disabled\n"); in ospi_dac_read()
1711 qemu_log_mask(LOG_GUEST_ERROR, "OSPI AHB wr while DAC disabled\n"); in ospi_dac_write()
1714 qemu_log_mask(LOG_GUEST_ERROR, "OSPI AHB wr while OSPI disabled\n"); in ospi_dac_write()
/qemu/hw/pci-host/
H A Ddesignware.c85 * AHB/AXI bus like any other PCI-device-initiated DMA read. in designware_pcie_root_msi_read()
/qemu/hw/usb/
H A Dhcd-dwc3.c5 * registers control the AXI/AHB interfaces properties, external FIFO support

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