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Searched +full:addr +full:- +full:gpios (Results 1 – 18 of 18) sorted by relevance

/qemu/hw/gpio/
H A Dtrace-events4 imx_gpio_read(const char *id, const char *reg, uint32_t value) "%s:[%s] -> 0x%" PRIx32
5 imx_gpio_write(const char *id, const char *reg, uint32_t value) "%s:[%s] <- 0x%" PRIx32
6 imx_gpio_set(const char *id, int line, int level) "%s:[%d] <- %d"
22 pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-15 [%s]"
23 …ription, unsigned id, unsigned prev_state, unsigned current_state) "%s GPIO id:%u status: %u -> %u"
45 stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 " "
46 stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s addr: 0x%" PRIx64 " val: 0x%…
H A Dnpcm7xx_gpio.c20 #include "hw/qdev-properties.h"
28 /* 32-bit register indices. */
70 uint32_t din_new = s->regs[NPCM7XX_GPIO_DIN]; in npcm7xx_gpio_update_events()
73 s->regs[NPCM7XX_GPIO_EVST] |= din_new & ~s->regs[NPCM7XX_GPIO_EVTYP]; in npcm7xx_gpio_update_events()
75 s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & s->regs[NPCM7XX_GPIO_EVTYP] in npcm7xx_gpio_update_events()
76 & s->regs[NPCM7XX_GPIO_EVBE]); in npcm7xx_gpio_update_events()
78 s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & din_new in npcm7xx_gpio_update_events()
79 & s->regs[NPCM7XX_GPIO_EVTYP]); in npcm7xx_gpio_update_events()
81 trace_npcm7xx_gpio_update_events(DEVICE(s)->canonical_path, in npcm7xx_gpio_update_events()
82 s->regs[NPCM7XX_GPIO_EVST], in npcm7xx_gpio_update_events()
[all …]
/qemu/hw/misc/macio/
H A Dgpio.c5 * Copyright (c) 2018 Mark Cave-Ayland
27 #include "hw/qdev-properties.h"
49 if (s->gpio_regs[gpio] & OUT_ENABLE) { in macio_set_gpio()
54 new_reg = s->gpio_regs[gpio] & ~IN_DATA; in macio_set_gpio()
59 if (new_reg == s->gpio_regs[gpio]) { in macio_set_gpio()
63 s->gpio_regs[gpio] = new_reg; in macio_set_gpio()
69 * For now, we hard wire known GPIOs in macio_set_gpio()
77 qemu_irq_raise(s->gpio_extirqs[gpio]); in macio_set_gpio()
80 qemu_irq_lower(s->gpio_extirqs[gpio]); in macio_set_gpio()
88 qemu_irq_raise(s->gpio_extirqs[gpio]); in macio_set_gpio()
[all …]
H A Dmacio.c4 * Copyright (c) 2005-2007 Fabrice Bellard
32 #include "hw/qdev-properties.h"
44 * The mac-io has two interfaces to the ESCC. One is called "escc-legacy",
47 * The magic below creates memory aliases to spawn the escc-legacy device
56 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->escc); in macio_escc_legacy_setup()
72 memory_region_init(escc_legacy, OBJECT(s), "escc-legacy", 256); in macio_escc_legacy_setup()
75 memory_region_init_alias(port, OBJECT(s), "escc-legacy-port", in macio_escc_legacy_setup()
81 memory_region_add_subregion(&s->bar, 0x12000, escc_legacy); in macio_escc_legacy_setup()
86 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->escc); in macio_bar_setup()
89 memory_region_add_subregion(&s->bar, 0x13000, bar); in macio_bar_setup()
[all …]
/qemu/system/
H A Dqtest.c10 * See the COPYING file in the top-level directory.
18 #include "chardev/char-fe.h"
22 #include "hw/qdev-core.h"
26 #include "system/cpu-timers.h"
27 #include "qemu/config-file.h"
29 #include "qemu/error-report.h"
86 * .. code-block:: none
94 * .. code-block:: none
101 * .. code-block:: none
111 * .. code-block:: none
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/qemu/hw/misc/
H A Dxlnx-zynqmp-apu-ctrl.c4 * Copyright (c) 2013-2022 Xilinx Inc
5 * SPDX-License-Identifier: GPL-2.0-or-later
15 #include "hw/qdev-properties.h"
22 #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
33 wfi_pending = s->cpu_pwrdwn_req & s->cpu_in_wfi; in update_wfi_out()
35 qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i))); in update_wfi_out()
41 XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque); in zynqmp_apu_rvbar_post_write()
45 uint64_t rvbar = s->regs[R_RVBARADDR0L + 2 * i] + in zynqmp_apu_rvbar_post_write()
46 ((uint64_t)s->regs[R_RVBARADDR0H + 2 * i] << 32); in zynqmp_apu_rvbar_post_write()
47 if (s->cpus[i]) { in zynqmp_apu_rvbar_post_write()
[all …]
/qemu/hw/arm/
H A Dfsl-imx31.c2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
6 * Based on hw/arm/fsl-imx31.c
24 #include "hw/arm/fsl-imx31.h"
26 #include "system/address-spaces.h"
27 #include "hw/qdev-properties.h"
29 #include "target/arm/cpu-qom.h"
36 object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm1136")); in fsl_imx31_init()
38 object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC); in fsl_imx31_init()
40 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX31_CCM); in fsl_imx31_init()
43 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL); in fsl_imx31_init()
[all …]
H A Dnrf51_soc.c8 * the COPYING file in the top-level directory.
15 #include "hw/qdev-clock.h"
24 * are supported in the future, add a sub-class of NRF51SoC for
37 static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) in clock_read() argument
40 __func__, addr, size); in clock_read()
44 static void clock_write(void *opaque, hwaddr addr, uint64_t data, in clock_write() argument
47 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", in clock_write()
48 __func__, addr, data, size); in clock_write()
64 if (!s->board_memory) { in nrf51_soc_realize()
73 if (clock_has_source(s->sysclk)) { in nrf51_soc_realize()
[all …]
H A Dfsl-imx25.c2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
6 * Based on hw/arm/xlnx-zynqmp.c
27 #include "hw/arm/fsl-imx25.h"
29 #include "hw/qdev-properties.h"
31 #include "target/arm/cpu-qom.h"
40 object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm926")); in fsl_imx25_init()
42 object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC); in fsl_imx25_init()
44 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX25_CCM); in fsl_imx25_init()
47 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL); in fsl_imx25_init()
51 object_initialize_child(obj, "gpt[*]", &s->gpt[i], TYPE_IMX25_GPT); in fsl_imx25_init()
[all …]
H A Dfsl-imx6.c2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
6 * Based on hw/arm/fsl-imx31.c
24 #include "hw/arm/fsl-imx6.h"
26 #include "hw/usb/imx-usb-phy.h"
28 #include "hw/qdev-properties.h"
31 #include "qemu/error-report.h"
33 #include "target/arm/cpu-qom.h"
46 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) { in fsl_imx6_init()
48 object_initialize_child(obj, name, &s->cpu[i], in fsl_imx6_init()
49 ARM_CPU_TYPE_NAME("cortex-a9")); in fsl_imx6_init()
[all …]
H A Darmv7m.c4 * Copyright (c) 2006-2007 CodeSourcery.
16 #include "hw/qdev-properties.h"
17 #include "hw/qdev-clock.h"
20 #include "qemu/error-report.h"
25 #include "target/arm/cpu-features.h"
26 #include "target/arm/cpu-qom.h"
34 return s->base | (offset & 0x1ffffff) >> 5; in bitband_addr()
44 hwaddr addr; in bitband_read() local
49 addr = bitband_addr(s, offset) & (-size); in bitband_read()
50 res = address_space_read(&s->source_as, addr, attrs, buf, size); in bitband_read()
[all …]
H A Dfsl-imx8mp.c4 * Based on hw/arm/fsl-imx6.c
8 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "system/address-spaces.h"
14 #include "hw/arm/fsl-imx8mp.h"
19 #include "target/arm/cpu-qom.h"
24 hwaddr addr; member
58 /* AIPS-5 Begin */
80 /* AIPS-5 End */
82 /* AIPS-4 Begin */
98 /* AIPS-4 End */
[all …]
H A Dstm32l4x5_soc.c4 * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
21 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
27 #include "system/address-spaces.h"
29 #include "hw/or-irq.h"
33 #include "hw/qdev-clock.h"
49 * Some IRQs are connected to the same CPU IRQ (denoted by -1)
[all …]
H A Darmsse.c23 #include "hw/arm/armsse-version.h"
26 #include "hw/qdev-clock.h"
29 * The SSE-300 puts some devices in different places to the
30 * SSE-200 (and original IoTKit). We use an array of these structs
36 #define NO_IRQ -1
37 #define NO_PPC -1
50 hwaddr addr; member
54 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */
86 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
98 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
[all …]
H A Domap1.c4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
22 #include "qemu/error-report.h"
23 #include "qemu/main-loop.h"
26 #include "system/address-spaces.h"
29 #include "hw/qdev-properties.h"
44 #include "target/arm/cpu-qom.h"
47 static inline void omap_log_badwidth(const char *funcname, hwaddr addr, int sz) in omap_log_badwidth() argument
49 qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx "\n", in omap_log_badwidth()
50 funcname, 8 * sz, addr); in omap_log_badwidth()
54 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr) in omap_badwidth_read8() argument
[all …]
/qemu/hw/ppc/
H A De500.c2 * QEMU PowerPC e500-based platforms
20 #include "qemu/guest-random.h"
24 #include "e500-ccsr.h"
26 #include "qemu/config-file.h"
28 #include "hw/char/serial-mm.h"
30 #include "system/block-backend-io.h"
40 #include "hw/qdev-properties.h"
44 #include "qemu/host-utils.h"
46 #include "hw/pci-host/ppce500.h"
47 #include "qemu/error-report.h"
[all …]
/qemu/hw/riscv/
H A Dmicrochip_pfsoc.c2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
13 * 2) eNVM (Embedded Non-Volatile Memory)
14 * 3) MMUARTs (Multi-Mode UART)
38 #include "qemu/error-report.h"
60 * See https://github.com/polarfire-soc/hart-software-services
74 * https://www.microsemi.com/document-portal/doc_download/
75 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
79 * https://www.microsemi.com/document-portal/doc_download/
80 * 1244581-polarfire-soc-register-map, contains the following 2 major parts:
81 * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm
[all …]
/qemu/pc-bios/
HDu-boot.e500 ... --------------------- ...