Searched +full:u54 +full:- +full:mc +full:- +full:rvcoreip (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause4 ---5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: SiFive Platform-Level Interrupt Controller (PLIC)11 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller12 (PLIC) high-level specification in the RISC-V Privileged Architecture17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two20 Each interrupt can be enabled on per-context basis. Any context can claim28 While the PLIC supports both edge-triggered and level-triggered interrupts,[all …]
1 // SPDX-License-Identifier: GPL-2.023 * This driver implements a version of the RISC-V PLIC with the actual layout26 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf28 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is29 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged87 u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32); in plic_toggle()90 raw_spin_lock(&handler->enable_lock); in plic_toggle()95 raw_spin_unlock(&handler->enable_lock); in plic_toggle()104 writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_toggle()108 if (handler->present && in plic_irq_toggle()[all …]