1 // SPDX-License-Identifier: GPL-2.0
23  * This driver implements a version of the RISC-V PLIC with the actual layout
26  *     https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
28  * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
29  * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
87 	u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32);  in plic_toggle()
90 	raw_spin_lock(&handler->enable_lock);  in plic_toggle()
95 	raw_spin_unlock(&handler->enable_lock);  in plic_toggle()
104 	writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);  in plic_irq_toggle()
108 		if (handler->present &&  in plic_irq_toggle()
109 		    cpumask_test_cpu(cpu, &handler->priv->lmask))  in plic_irq_toggle()
110 			plic_toggle(handler, d->hwirq, enable);  in plic_irq_toggle()
120 	cpumask_and(&amask, &priv->lmask, cpu_online_mask);  in plic_irq_unmask()
132 	plic_irq_toggle(&priv->lmask, d, 0);  in plic_irq_mask()
143 	cpumask_and(&amask, &priv->lmask, mask_val);  in plic_set_affinity()
151 		return -EINVAL;  in plic_set_affinity()
153 	plic_irq_toggle(&priv->lmask, d, 0);  in plic_set_affinity()
166 	writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);  in plic_irq_eoi()
182 	struct plic_priv *priv = d->host_data;  in plic_irqdomain_map()
184 	irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,  in plic_irqdomain_map()
187 	irq_set_affinity(irq, &priv->lmask);  in plic_irqdomain_map()
219  * Handling an interrupt is a two-step process: first you claim the interrupt
228 	void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;  in plic_handle_irq()
231 	WARN_ON_ONCE(!handler->present);  in plic_handle_irq()
236 		int irq = irq_find_mapping(handler->priv->irqdomain, hwirq);  in plic_handle_irq()
251 	writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);  in plic_set_threshold()
286 		return -ENOMEM;  in plic_init()
288 	priv->regs = of_iomap(node, 0);  in plic_init()
289 	if (WARN_ON(!priv->regs)) {  in plic_init()
290 		error = -EIO;  in plic_init()
294 	error = -EINVAL;  in plic_init()
303 	error = -ENOMEM;  in plic_init()
304 	priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1,  in plic_init()
306 	if (WARN_ON(!priv->irqdomain))  in plic_init()
347 		 * When running in M-mode we need to ignore the S-mode handler.  in plic_init()
352 		if (handler->present) {  in plic_init()
358 		cpumask_set_cpu(cpu, &priv->lmask);  in plic_init()
359 		handler->present = true;  in plic_init()
360 		handler->hart_base =  in plic_init()
361 			priv->regs + CONTEXT_BASE + i * CONTEXT_PER_HART;  in plic_init()
362 		raw_spin_lock_init(&handler->enable_lock);  in plic_init()
363 		handler->enable_base =  in plic_init()
364 			priv->regs + ENABLE_BASE + i * ENABLE_PER_HART;  in plic_init()
365 		handler->priv = priv;  in plic_init()
377 	if (handler->present && !plic_cpuhp_setup_done) {  in plic_init()
389 	iounmap(priv->regs);  in plic_init()
395 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);