Searched full:socs (Results 1 – 25 of 26) sorted by relevance
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4 The `Nuvoton iBMC`_ chips are a family of Arm-based SoCs that are27 There are also two more SoCs, NPCM710 and NPCM705, which are single-core
4 Xilinx Versal is a family of heterogeneous multi-core SoCs12 The family of Versal SoCs share a single architecture but come in
27 /* These type names are for specific SoCs; other than instantiating
4 adaptive SoCs and FPGAs. The MicroBlaze™ V processor is based on the 32-bit (or
3 # Functional test that boots the ASPEED SoCs with firmware
9 on FPGAs. These SoCs are based on the same core architecture as the or1ksim
14 many different companies with different devices, and these SoCs are
8 on a chip (SoCs). Configuration of these is often a source of
17 many different companies with different devices, and these SoCs are
2 * GPIO Controller for a lot of Freescale SoCs
202 * and inserting it into another. This is useful for SoCs like the
147 these SoCs are e500v2 based MPC85xx series, hence you cannot test anything
3 * Microsemi's SmartFusion2 and SmartFusion SoCs.
2 * QEMU model of the UART on the SiFive E300 and U500 series SOCs.
21 * 4xx SoCs, such as the 440EP.
3 * This is found in some 440 SoCs e.g. the 460EX.
393 * The boot block starting from 0.0.6 for NPCM8xx SoCs stores the DRAM size in npcm_gcr_realize()
272 * To maintain compatibility with older SoCs such as the AST2600, in hash_prepare_sg_iov()
15 AMD secure processor (AMD-SP), which is present in AMD SOCs. Firmware running
1067 emulates their SoCs was very old and unmaintained. This code was1073 for all machine types using the PXA2xx and OMAP2 SoCs. We are also
1395 * Not all combinations are valid, and different SoCs may support different1418 * This layout is transferrable between Amlogic SoCs supporting this modifier.1431 * Amlogic SoCs supporting this modifier.
588 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ in aspeed_soc_ast2600_realize()