Home
last modified time | relevance | path

Searched full:slcr (Results 1 – 17 of 17) sorted by relevance

/linux-6.15/arch/arm/mach-zynq/
Dslcr.c3 * Xilinx SLCR driver
33 * zynq_slcr_write - Write to a register in SLCR block
36 * @offset: Register offset in SLCR block
46 * zynq_slcr_read - Read a register in SLCR block
48 * @val: Pointer to value to be read from SLCR
49 * @offset: Register offset in SLCR block
59 * zynq_slcr_unlock - Unlock SLCR registers
188 * zynq_early_slcr_init - Early slcr init function
192 * Called very early during boot from platform code to unlock SLCR.
198 np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); in zynq_early_slcr_init()
[all …]
DMakefile7 obj-y := common.o slcr.o pm.o
Dplatsmp.c36 /* MS: Expectation that SLCR are directly map and accessible */ in zynq_cpun_start()
/linux-6.15/drivers/pci/controller/dwc/
Dpcie-amd-mdb.c56 * @slcr: MDB System Level Control and Status Register (SLCR) base
63 void __iomem *slcr; member
88 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC); in amd_mdb_intx_irq_mask()
108 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC); in amd_mdb_intx_irq_unmask()
148 val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC); in dw_pcie_rp_intx()
183 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC); in amd_mdb_event_irq_mask()
197 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC); in amd_mdb_event_irq_unmask()
228 val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC); in amd_mdb_pcie_event()
229 val &= ~readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_MASK_MISC); in amd_mdb_pcie_event()
232 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC); in amd_mdb_pcie_event()
[all …]
/linux-6.15/drivers/reset/
Dreset-zynq.c21 struct regmap *slcr; member
40 return regmap_update_bits(priv->slcr, in zynq_reset_assert()
57 return regmap_update_bits(priv->slcr, in zynq_reset_deassert()
76 ret = regmap_read(priv->slcr, priv->offset + (bank * 4), &reg); in zynq_reset_status()
98 priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in zynq_reset_probe()
100 if (IS_ERR(priv->slcr)) { in zynq_reset_probe()
101 dev_err(&pdev->dev, "unable to get zynq-slcr regmap"); in zynq_reset_probe()
102 return PTR_ERR(priv->slcr); in zynq_reset_probe()
/linux-6.15/Documentation/devicetree/bindings/reset/
Dzynq-reset.txt9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
11 This should be a phandle to the Zynq's SLCR registers.
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
21 syscon = <&slcr>;
/linux-6.15/drivers/fpga/
Dzynq-fpga.c27 /* Offsets into SLCR regmap */
110 /* Masks for controlling stuff in SLCR */
127 struct regmap *slcr; member
286 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_init()
290 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
293 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
513 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_complete()
517 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_complete()
569 priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node, in zynq_fpga_probe()
571 if (IS_ERR(priv->slcr)) { in zynq_fpga_probe()
[all …]
/linux-6.15/Documentation/devicetree/bindings/pci/
Damd,versal2-mdb-host.yaml22 - description: MDB System Level Control and Status Register (SLCR) Base
29 - const: slcr
100 reg-names = "slcr", "config", "dbi", "atu";
Dsnps,dw-pcie.yaml116 - description: AMD MDB PCIe SLCR region
117 const: slcr
/linux-6.15/Documentation/devicetree/bindings/fpga/
Dxilinx-zynq-fpga-mgr.yaml32 Phandle to syscon block which provide access to SLCR registers
51 syscon = <&slcr>;
/linux-6.15/Documentation/devicetree/bindings/pinctrl/
Dxlnx,pinctrl-zynq.yaml34 description: Specifies the base address and size of the SLCR space.
39 phandle to the SLCR.
186 syscon = <&slcr>;
/linux-6.15/arch/arm/boot/dts/xilinx/
Dzynq-7000.dtsi334 slcr: slcr@f8000000 { label
338 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
364 syscon = <&slcr>;
370 syscon = <&slcr>;
399 syscon = <&slcr>;
/linux-6.15/drivers/clk/zynq/
Dclkc.c580 struct device_node *slcr; in zynq_clock_init() local
594 slcr = of_get_parent(np); in zynq_clock_init()
596 if (slcr->data) { in zynq_clock_init()
597 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; in zynq_clock_init()
600 of_node_put(slcr); in zynq_clock_init()
606 of_node_put(slcr); in zynq_clock_init()
/linux-6.15/drivers/pci/controller/
Dpcie-xilinx-cpm.c108 * @cpm_base: CPM System Level Control and Status Register(SLCR) Base
303 * CPM SLCR block. in xilinx_cpm_pcie_event_flow()
501 * CPM SLCR block. in xilinx_cpm_pcie_init_port()
/linux-6.15/Documentation/devicetree/bindings/clock/
Dzynq-7000.txt17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
/linux-6.15/drivers/net/ethernet/mellanox/mlxsw/
Dreg.h1293 /* SLCR - Switch LAG Configuration 2 Register
1301 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1315 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1324 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12);
1336 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1396 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1402 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1406 MLXSW_REG_ZERO(slcr, payload); in mlxsw_reg_slcr_pack()
13016 MLXSW_REG(slcr),
Dspectrum.c2641 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); in mlxsw_sp_lag_init()