56  * @slcr: MDB System Level Control and Status Register (SLCR) base
63 	void __iomem			*slcr;  member
88 	writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC);  in amd_mdb_intx_irq_mask()
108 	writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC);  in amd_mdb_intx_irq_unmask()
148 	val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);  in dw_pcie_rp_intx()
183 	writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC);  in amd_mdb_event_irq_mask()
197 	writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC);  in amd_mdb_event_irq_unmask()
228 	val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);  in amd_mdb_pcie_event()
229 	val &= ~readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_MASK_MISC);  in amd_mdb_pcie_event()
232 	writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);  in amd_mdb_pcie_event()
256 		       pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC);  in amd_mdb_pcie_init_port()
259 	val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);  in amd_mdb_pcie_init_port()
261 	writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);  in amd_mdb_pcie_init_port()
265 		       pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC);  in amd_mdb_pcie_init_port()
413 	pcie->slcr = devm_platform_ioremap_resource_byname(pdev, "slcr");  in amd_mdb_add_pcie_port()
414 	if (IS_ERR(pcie->slcr))  in amd_mdb_add_pcie_port()
415 		return PTR_ERR(pcie->slcr);  in amd_mdb_add_pcie_port()