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Searched full:plls (Results 1 – 15 of 15) sorted by relevance

/qemu/hw/misc/
H A Dbcm2835_cprman.c11 * - the PLLs
15 * A main oscillator (xosc) feeds all the PLLs. Each PLLs has one or more
24 * dividers (and multipliers in case of the PLLs), and can be disabled (in this
454 r |= pll_is_locked(&s->plls[i]) << CM_LOCK_MAPPING[i]; in get_cm_lock()
487 pll_update_all_channels(s, &s->plls[i]); in update_pll_and_channels_from_cm()
554 pll_update(&s->plls[CPRMAN_PLLA]); in cprman_write()
558 pll_update(&s->plls[CPRMAN_PLLC]); in cprman_write()
562 pll_update(&s->plls[CPRMAN_PLLD]); in cprman_write()
566 pll_update(&s->plls[CPRMAN_PLLH]); in cprman_write()
570 pll_update(&s->plls[CPRMAN_PLLB]); in cprman_write()
[all …]
H A Dstm32l4x5_rcc.c430 pll_set_enable(&s->plls[RCC_PLL_PLLSAI2], val); in rcc_update_cr_register()
439 pll_set_enable(&s->plls[RCC_PLL_PLLSAI1], val); in rcc_update_cr_register()
452 pll_set_enable(&s->plls[RCC_PLL_PLL], val); in rcc_update_cr_register()
741 * The 3 PLLs share the same register layout
770 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P, in rcc_update_pllsaixcfgr()
773 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P, in rcc_update_pllsaixcfgr()
780 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_R, in rcc_update_pllsaixcfgr()
785 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_R, val); in rcc_update_pllsaixcfgr()
789 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_Q, in rcc_update_pllsaixcfgr()
794 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_Q, val); in rcc_update_pllsaixcfgr()
[all …]
H A Dnpcm_clk.c296 npcm7xx_clk_update_pll(&clk->plls[i]); in npcm7xx_clk_update_all_plls()
783 return clk->plls[index].clock_out; in npcm7xx_get_clock()
801 clock_set_source(clk->plls[i].clock_in, src); in npcm7xx_connect_clocks()
909 npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]); in npcm_clk_write()
991 &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL); in npcm7xx_clk_init_clock_hierarchy()
992 npcm7xx_init_clock_pll(&s->plls[i], s, in npcm7xx_clk_init_clock_hierarchy()
1045 if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) { in npcm_clk_realize()
H A Dimx8mp_analog.c73 /* all PLLs need to be locked */ in imx8mp_analog_reset()
H A Dzynq_slcr.c272 #define ZYNQ_COMPUTE_CLK(state, plls, reg, enable_field) \ argument
273 zynq_slcr_compute_clock((plls), (state)->regs[reg], \
H A Dimx7_ccm.c49 /* all PLLs need to be locked */ in imx7_analog_reset()
H A Dimx6_ccm.c455 /* all PLLs need to be locked */ in imx6_ccm_reset()
H A Dimx6ul_ccm.c610 /* all PLLs need to be locked */ in imx6ul_ccm_reset()
H A Daspeed_scu.c701 /* PLLs are always "locked" */ in aspeed_ast2600_scu_read()
/qemu/include/hw/misc/
H A Dstm32l4x5_rcc.h227 /* PLLs */
228 RccPllState plls[RCC_NUM_PLL]; member
H A Dnpcm_clk.h36 /* PLLs in CLK module. */
170 NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS]; member
H A Dbcm2835_cprman.h198 CprmanPllState plls[CPRMAN_NUM_PLL]; member
H A Dbcm2835_cprman_internals.h31 /* PLLs */
/qemu/tests/qtest/
H A Dstm32l4x5_rcc-test.c170 * These test separately that we can enable the plls, change the sysclk, in main()
/qemu/docs/system/riscv/
H A Dsifive_u.rst102 2. First Stage Boot Loader (FSBL), which brings up PLLs and DDR memory.