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Searched full:otp (Results 1 – 22 of 22) sorted by relevance

/qemu/include/hw/nvram/
H A Dbcm2835_otp.h2 * BCM2835 One-Time Programmable (OTP) Memory
15 #define TYPE_BCM2835_OTP "bcm2835-otp"
20 /* https://elinux.org/BCM2835_registers#OTP */
37 /* Lock OTP Programming (Customer OTP and private key) */
40 /* -- Row 36-43: Customer OTP -- */
45 /* Magic numbers to lock programming of customer OTP and private key */
H A Dnpcm7xx_otp.h2 * Nuvoton NPCM7xx OTP (Fuse Array) Interface
22 /* Each OTP module holds 8192 bits of one-time programmable storage */
44 * struct NPCM7xxOTPState - Device state for one OTP module.
48 * @array: OTP storage array.
58 #define TYPE_NPCM7XX_OTP "npcm7xx-otp"
67 * npcm7xx_otp_array_write - ECC encode and write data to OTP array.
68 * @s: OTP module.
70 * @offset: Offset of first byte to be written in the OTP array.
/qemu/hw/nvram/
H A Dnpcm7xx_otp.c2 * Nuvoton NPCM7xx OTP (Fuse Array) Interface
62 * struct NPCM7xxOTPClass - OTP module class.
66 * The two OTP modules (key-storage and fuse-array) have slightly different
106 /* Common register read handler for both OTP classes. */
134 /* Read a byte from the OTP array into the data register. */
143 /* Program a byte from the data register into the OTP array. */
175 /* Common register write handler for both OTP classes. */
253 /* Register read handler specific to the fuse array OTP module. */
263 * work the same way for both kinds of OTP modules. in npcm7xx_fuse_array_read()
268 /* FUSTRAP is stored as three copies in the OTP array. */ in npcm7xx_fuse_array_read()
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H A Dbcm2835_otp.c2 * BCM2835 One-Time Programmable (OTP) Memory
4 * The OTP implementation is mostly a stub except for the OTP rows
7 * The OTP registers are unimplemented due to lack of documentation.
19 /* OTP rows are 1-indexed */
32 /* Real OTP rows work as e-fuses */ in bcm2835_otp_set_row()
/qemu/hw/misc/
H A Dbcm2835_property.c329 /* Customer OTP */ in bcm2835_property_mbox_push()
340 uint32_t otp_row = bcm2835_otp_get_row(s->otp, in bcm2835_property_mbox_push()
354 /* Magic numbers to permanently lock customer OTP */ in bcm2835_property_mbox_push()
357 bcm2835_otp_set_row(s->otp, in bcm2835_property_mbox_push()
364 if (bcm2835_otp_get_row(s->otp, BCM2835_OTP_ROW_32) & in bcm2835_property_mbox_push()
373 bcm2835_otp_set_row(s->otp, in bcm2835_property_mbox_push()
389 uint32_t otp_row = bcm2835_otp_get_row(s->otp, in bcm2835_property_mbox_push()
404 if (bcm2835_otp_get_row(s->otp, BCM2835_OTP_ROW_32) & in bcm2835_property_mbox_push()
413 bcm2835_otp_set_row(s->otp, in bcm2835_property_mbox_push()
545 obj = object_property_get_link(OBJECT(dev), "otp", &error_abort); in bcm2835_property_realize()
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H A Dsifive_u_otp.c2 * QEMU SiFive U OTP (One-Time Programmable) Memory interface
6 * Simple model of the OTP to emulate register reads made by the SDK BSP
221 error_setg(errp, "OTP drive size < 16K"); in sifive_u_otp_realize()
/qemu/tests/functional/
H A Dtest_arm_aspeed_ast1030.py52 'otp info conf',
53 'otp info scu',
/qemu/hw/arm/
H A Dbcm2835_peripherals.c119 /* OTP */ in raspi_peripherals_base_init()
120 object_initialize_child(obj, "bcm2835-otp", &s->otp, in raspi_peripherals_base_init()
135 object_property_add_const_link(OBJECT(&s->property), "otp", in raspi_peripherals_base_init()
136 OBJECT(&s->otp)); in raspi_peripherals_base_init()
383 /* OTP */ in bcm_soc_peripherals_common_realize()
384 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { in bcm_soc_peripherals_common_realize()
389 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->otp), 0)); in bcm_soc_peripherals_common_realize()
H A Dnpcm8xx.c40 /* OTP fuse array */
421 object_initialize_child(obj, "otp", &s->fuse_array, in npcm8xx_init()
555 /* OTP fuse strap array. Cannot fail. */ in npcm8xx_realize()
H A Dnpcm7xx.c39 /* OTP key storage and fuse strap array */
539 /* OTP key storage and fuse strap array. Cannot fail. */ in npcm7xx_realize()
/qemu/include/hw/misc/
H A Dsifive_u_otp.h2 * QEMU SiFive U OTP (One-Time Programmable) Memory interface
55 #define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp"
H A Dbcm2835_property.h30 BCM2835OTPState *otp; member
H A Dbcm2835_cprman_internals.h629 .name = "otp",
632 FILL_CLOCK_MUX_INIT_INFO(OTP, xosc),
/qemu/hw/riscv/
H A Dsifive_u.c15 * 5) OTP (One-Time Programmable) memory with stored serial number
222 nodename = g_strdup_printf("/soc/otp@%lx", in create_fdt()
230 "sifive,fu540-c000-otp"); in create_fdt()
774 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); in type_init()
891 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); in sifive_u_soc_realize()
892 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { in sifive_u_soc_realize()
895 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); in sifive_u_soc_realize()
H A Dsifive_e.c16 * The OTP ROM and Flash boot code will be emulated in a future version.
/qemu/docs/system/riscv/
H A Dsifive_u.rst22 * 1 One-Time Programmable (OTP) memory with stored serial number
74 SiFive reserves the first 1 KiB of the 16 KiB OTP memory for internal use.
76 offset 0xfc. U-Boot reads the serial number from the OTP memory, and uses
/qemu/include/hw/arm/
H A Dbcm2835_peripherals.h75 BCM2835OTPState otp; member
/qemu/include/hw/riscv/
H A Dsifive_u.h50 SiFiveUOTPState otp; member
/qemu/docs/system/arm/
H A Dnuvoton.rst48 * OTP controllers (no protection features)
/qemu/docs/about/
H A Dremoved-features.rst425 ``-drive if=none`` for the sifive_u OTP device (removed in 8.0)
428 Use ``-drive if=pflash`` to configure the OTP device of the sifive_u
/qemu/hw/sd/
H A Dsd.c2392 /* Copy flag (OTP) & Permanent write protect */ in sd_write_byte()
/qemu/tests/data/qobject/
H A Dqdict.txt1771 bfin-otp.c: 4874