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/linux-6.8/Documentation/devicetree/bindings/
Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
31 - enum:
33 - acbel,fsg032
34 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
35 - ad,ad7414
[all …]
/linux-6.8/drivers/eisa/
Deisa.ids6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
25 ACE7010 "ACME Multi-Function Board"
39 ACR1711 "AcerFrame 1000 486/33 SYSTEM-2"
41 ACR3211 "AcerFrame 3000MP 486 SYSTEM-1"
[all …]
/linux-6.8/drivers/edac/
Dfsl_ddr_edac.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
6 * ARM-based Layerscape SoCs including LS2xxx and LS1021A. Originally
11 * 2006-2007 (c) MontaVista Software, Inc.
54 #define DDR_EIE_SBEE 0x4 /* single-bit ECC error */
55 #define DDR_EIE_MBEE 0x8 /* multi-bit ECC error */
59 #define DDR_EDE_SBE 0x4 /* single-bit ECC error */
60 #define DDR_EDE_MBE 0x8 /* multi-bit ECC error */
65 #define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */
66 #define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */
/linux-6.8/drivers/media/dvb-frontends/drx39xyj/
Ddrx_dap_fasi.h2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
48 /*-------- compilation control switches --------------------------------------*/
53 /*-------- Required includes -------------------------------------------------*/
57 /*-------- Defines, configuring the API --------------------------------------*/
98 #error At least one of short- or long-addressing format must be allowed.
103 * Single/master multi master setting
106 * Comments about SINGLE MASTER/MULTI MASTER modes:
113 * + multi master mode means use of repeated starts
118 * Single/multi master selected via the flags in the FASI protocol.
121 * Default is single master, DAP FASI changes multi-master setting silently
[all …]
/linux-6.8/Documentation/devicetree/bindings/display/
Dmulti-inno,mi0283qt.txt1 Multi-Inno MI0283QT display panel
4 - compatible: "multi-inno,mi0283qt".
7 all mandatory properties described in ../spi/spi-bus.txt must be specified.
10 - dc-gpios: D/C pin. The presence/absence of this GPIO determines
12 - present: IM=x110 4-wire 8-bit data serial interface
13 - absent: IM=x101 3-wire 9-bit data serial interface
14 - reset-gpios: Reset pin
15 - power-supply: A regulator node for the supply voltage.
16 - backlight: phandle of the backlight device attached to the panel
17 - rotation: panel rotation in degrees counter clockwise (0,90,180,270)
[all …]
/linux-6.8/arch/parisc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T if !64BIT
37 select GENERIC_ATOMIC64 if !64BIT
79 select HAVE_DYNAMIC_FTRACE if $(cc-option,-fpatchable-function-entry=1,1)
86 select HAVE_FUNCTION_DESCRIPTORS if 64BIT
89 The PA-RISC microprocessor is designed by Hewlett-Packard and used
91 and later HP3000 series). The PA-RISC Linux project home page is
119 select GENERIC_BUG_RELATIVE_POINTERS if 64BIT
138 default 18 if 64BIT
145 default 18 if 64BIT
[all …]
/linux-6.8/arch/powerpc/kvm/
Dbook3s_hv_ras.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #define SRR1_MC_LDSTERR (1ul << (63-42))
22 #define SRR1_MC_IFETCH_SH (63-45)
25 #define SRR1_MC_IFETCH_SLBMULTI 3 /* SLB multi-hit */
26 #define SRR1_MC_IFETCH_SLBPARMULTI 4 /* SLB parity + multi-hit */
27 #define SRR1_MC_IFETCH_TLBMULTI 5 /* I-TLB multi-hit */
30 #define DSISR_MC_DERAT_MULTI 0x800 /* D-ERAT multi-hit */
31 #define DSISR_MC_TLB_MULTI 0x400 /* D-TLB multi-hit */
33 #define DSISR_MC_SLB_MULTI 0x080 /* SLB multi-hit */
34 #define DSISR_MC_SLB_PARMULTI 0x040 /* SLB parity + multi-hit */
[all …]
/linux-6.8/sound/pci/ctxfi/
Dctresource.c1 // SPDX-License-Identifier: GPL-2.0-only
21 /* Resource allocation based on bit-map management mechanism */
24 unsigned int multi, unsigned int *ridx) in get_resource() argument
29 for (i = 0, n = multi; i < amount; i++) { in get_resource()
33 n = multi; in get_resource()
36 if (!(--n)) in get_resource()
42 return -ENOENT; in get_resource()
45 /* Mark the contiguous bits in resource bit-map as used */ in get_resource()
46 for (n = multi; n > 0; n--) { in get_resource()
50 i--; in get_resource()
[all …]
/linux-6.8/drivers/gpu/drm/xe/
Dxe_tile.c1 // SPDX-License-Identifier: MIT
19 * DOC: Multi-tile Design
21 * Different vendors use the term "tile" a bit differently, but in the Intel
24 * that's what is referred to as a "multi-tile device." In such cases, pretty
25 * much all hardware is replicated per-tile, although certain responsibilities
27 * solely by the "root tile." A multi-tile platform takes care of tying the
29 * are forwarded to the root tile, the per-tile vram is combined into a single
38 * Historically most Intel devices were single-tile devices that contained a
39 * single GT. PVC is an example of an Intel platform built on a multi-tile
44 * single GPU. This is important from a software perspective because multi-GT
[all …]
Dxe_exec_queue_types.h1 /* SPDX-License-Identifier: MIT */
25 XE_EXEC_QUEUE_PRIORITY_UNSET = -2, /* For execlist usage only */
35 * struct xe_exec_queue - Execution queue
67 * @last_fence: last fence on exec queue, protected by vm->lock in write
68 * mode if bind exec queue, protected by dma resv lock if non-bind exec
74 #define EXEC_QUEUE_FLAG_BANNED BIT(0)
76 #define EXEC_QUEUE_FLAG_KERNEL BIT(1)
78 #define EXEC_QUEUE_FLAG_PERMANENT BIT(2)
80 #define EXEC_QUEUE_FLAG_PERSISTENT BIT(3)
82 #define EXEC_QUEUE_FLAG_VM BIT(4)
[all …]
/linux-6.8/arch/sh/mm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
9 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12 On other systems (such as the SH-3 and 4) where an MMU exists,
68 config 29BIT
69 def_bool !32BIT
72 config 32BIT
77 bool "Support 32-bit physical addressing through PMB"
79 select 32BIT
83 32-bits through the SH-4A PMB. If this is not set, legacy
84 29-bit physical addressing will be used.
[all …]
/linux-6.8/sound/soc/sof/
Dipc4-topology.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
14 #define SOF_IPC4_FW_PAGE_SIZE BIT(12)
15 #define SOF_IPC4_FW_PAGE(x) ((((x) + BIT(12) - 1) & ~(BIT(12) - 1)) >> 12)
16 #define SOF_IPC4_FW_ROUNDUP(x) (((x) + BIT(6) - 1) & (~(BIT(6) - 1)))
19 #define SOF_IPC4_MODULE_AUTO_START BIT(4)
22 * LL domain - Low latency domain
23 * DP domain - Data processing domain
26 #define SOF_IPC4_MODULE_LL BIT(5)
27 #define SOF_IPC4_MODULE_DP BIT(6)
28 #define SOF_IPC4_MODULE_LIB_CODE BIT(7)
[all …]
/linux-6.8/drivers/net/wireless/intel/iwlwifi/fw/api/
Dmac.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
11 * AUX indices follows - 1 for non-CDB, 2 for CDB.
31 * enum iwl_mac_protection_flags - MAC context flags
40 MAC_PROT_FLG_TGG_PROTECT = BIT(3),
41 MAC_PROT_FLG_HT_PROT = BIT(23),
42 MAC_PROT_FLG_FAT_PROT = BIT(24),
43 MAC_PROT_FLG_SELF_CTS_EN = BIT(30),
46 #define MAC_FLG_SHORT_SLOT BIT(4)
47 #define MAC_FLG_SHORT_PREAMBLE BIT(5)
[all …]
/linux-6.8/include/linux/soundwire/
Dsdw_intel.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
29 #define SDW_SHIM_LCTL_SPA BIT(0)
31 #define SDW_SHIM_LCTL_CPA BIT(8)
37 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
38 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
40 #define SDW_SHIM_SYNC_SYNCCPU BIT(15)
42 #define SDW_SHIM_SYNC_CMDSYNC BIT(16)
43 #define SDW_SHIM_SYNC_SYNCGO BIT(24)
68 #define SDW_SHIM_PCMSYCM_DIR BIT(15)
[all …]
/linux-6.8/Documentation/admin-guide/mm/
Dmultigen_lru.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Multi-Gen LRU
6 The multi-gen LRU is an alternative LRU implementation that optimizes
26 -----------
38 0x0001 The main switch for the multi-gen LRU.
39 0x0002 Clearing the accessed bit in leaf page table entries in large
42 disabled, the multi-gen LRU will suffer a minor performance
46 0x0004 Clearing the accessed bit in non-leaf page table entries as
49 disabled, the multi-gen LRU will suffer a negligible
65 --------------------
[all …]
/linux-6.8/drivers/iio/dac/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 tristate "Analog Devices AD5064 and similar multi-channel DAC driver"
24 AD5045, AD5064, AD5064-1, AD5065, AD5625, AD5625R, AD5627, AD5627R,
38 AD5362, AD5363, AD5370, AD5371, AD5373 multi-channel
51 AD5382, AD5383, AD5384, AD5390, AD5391, AD5392 multi-channel
61 Say yes here to build support for Analog Devices AD5421 loop-powered
62 digital-to-analog convertors (DAC).
149 tristate "Analog Devices AD5686 and similar multi-channel DACs (SPI)"
161 tristate "Analog Devices AD5696 and similar multi-channel DACs (I2C)"
174 tristate "Analog Devices AD5755/AD5755-1/AD5757/AD5735/AD5737 DAC driver"
[all …]
/linux-6.8/drivers/zorro/
Dzorro.ids4 # Maintained by Geert Uytterhoeven <zorro@linux-m68k.org>
12 # product product_name <-- single tab
23 0200 3-State
29 6700 A2386-SX [ISA Bus Bridge]
38 4500 A2232 Prototype [Multi I/O]
39 4600 A2232 [Multi I/O]
46 6700 A2386-SX [ISA Bus Bridge]
61 03ed A-Squared
70 0300 8-Up (Rev A) [RAM Expansion]
71 0400 8-Up (Rev Z) [RAM Expansion]
[all …]
/linux-6.8/Documentation/devicetree/bindings/dma/
Dsnps,dma-spear1340.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
21 - enum:
[all …]
/linux-6.8/drivers/pwm/
Dpwm-bcm-iproc.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #define IPROC_PWM_PRESCALE_SHIFT(ch) ((3 - (ch)) * \
51 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_enable()
53 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_enable()
55 /* must be a 400 ns delay between clearing and setting enable bit */ in iproc_pwmc_enable()
63 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_disable()
65 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_disable()
67 /* must be a 400 ns delay between clearing and setting enable bit */ in iproc_pwmc_disable()
75 u64 tmp, multi, rate; in iproc_pwmc_get_state() local
78 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_get_state()
[all …]
/linux-6.8/drivers/gpu/drm/tiny/
Dmi0283qt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DRM driver for Multi-Inno MI0283QT panels
46 #define ILI9341_MADCTL_BGR BIT(3)
47 #define ILI9341_MADCTL_MV BIT(5)
48 #define ILI9341_MADCTL_MX BIT(6)
49 #define ILI9341_MADCTL_MY BIT(7)
55 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev); in mi0283qt_enable()
56 struct mipi_dbi *dbi = &dbidev->dbi; in mi0283qt_enable()
60 if (!drm_dev_enter(pipe->crtc.dev, &idx)) in mi0283qt_enable()
116 * resets only on power-on and not on each reboot through in mi0283qt_enable()
[all …]
/linux-6.8/Documentation/sound/cards/
Dcmipci.rst2 Brief Notes on C-Media 8338/8738/8768/8770 Driver
8 Front/Rear Multi-channel Playback
9 ---------------------------------
13 DACs, both streams are handled independently unlike the 4/6ch multi-
22 - The first DAC supports U8 and S16LE formats, while the second DAC
24 - The second DAC supports only two channel stereo.
43 front one) and was so excited. It was even with "Four Channel" bit
51 control switch in the driver "Line-In As Rear", which you can change
52 via alsamixer or somewhat else. When this switch is on, line-in jack
60 4/6 Multi-Channel Playback
[all …]
/linux-6.8/Documentation/input/devices/
Dsentelic.rst8 :Copyright: |copy| 2002-2011 Sentelic Corporation.
10 :Last update: Dec-07-2011
27 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
28 BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
30 |---------------| |---------------| |---------------| |---------------|
34 Bit5 => Y sign bit
35 Bit4 => X sign bit
40 Byte 2: X Movement(9-bit 2's complement integers)
41 Byte 3: Y Movement(9-bit 2's complement integers)
43 valid values, -8 ~ +7
[all …]
/linux-6.8/drivers/ata/
Dpata_ftide010.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * struct ftide010 - state container for the Faraday FTIDE010
48 /* Gemini-specific properties */
76 /* Set this bit for UDMA mode 5 and 6 */
77 #define FTIDE010_UDMA_TIMING_MODE_56 BIT(7)
80 #define FTIDE010_CLK_MOD_DEV0_CLK_SEL BIT(0)
81 #define FTIDE010_CLK_MOD_DEV1_CLK_SEL BIT(1)
83 #define FTIDE010_CLK_MOD_DEV0_UDMA_EN BIT(4)
84 #define FTIDE010_CLK_MOD_DEV1_UDMA_EN BIT(5)
102 * mdma_50_active_time: array of 4 elements for Td timing for multi
[all …]
/linux-6.8/Documentation/devicetree/bindings/leds/
Dallwinner,sun50i-a100-ledc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/leds/allwinner,sun50i-a100-ledc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Samuel Holland <samuel@sholland.org>
13 The LED controller found in Allwinner sunxi SoCs uses a one-wire serial
19 - const: allwinner,sun50i-a100-ledc
20 - items:
21 - enum:
22 - allwinner,sun20i-d1-ledc
[all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/amdzen1/
Dfloating-point.json5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
20 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.",
27 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.",
34 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
[all …]

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