linux/soundwire/sdw_intel.h

1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
29 #define SDW_SHIM_LCTL_SPA		BIT(0)
31 #define SDW_SHIM_LCTL_CPA		BIT(8)
37 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)
38 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)
40 #define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
42 #define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
43 #define SDW_SHIM_SYNC_SYNCGO		BIT(24)
68 #define SDW_SHIM_PCMSYCM_DIR		BIT(15)
73 #define SDW_SHIM_IOCTL_MIF		BIT(0)
74 #define SDW_SHIM_IOCTL_CO		BIT(1)
75 #define SDW_SHIM_IOCTL_COE		BIT(2)
76 #define SDW_SHIM_IOCTL_DO		BIT(3)
77 #define SDW_SHIM_IOCTL_DOE		BIT(4)
78 #define SDW_SHIM_IOCTL_BKE		BIT(5)
79 #define SDW_SHIM_IOCTL_WPDD		BIT(6)
80 #define SDW_SHIM_IOCTL_CIBD		BIT(8)
81 #define SDW_SHIM_IOCTL_DIBD		BIT(9)
86 #define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
91 #define SDW_SHIM_WAKESTS_STATUS		BIT(0)
96 #define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
97 #define SDW_SHIM_CTMCTL_DODS		BIT(1)
109  * ACE2.x definitions for SHIM registers - only accessible when the
118 /* Read-only capabilities */
120 #define SDW_SHIM2_LECAP_HDS		BIT(0)		/* unset -> Host mode */
125 #define SDW_SHIM2_PCMSCAP_ISS		GENMASK(3, 0)	/* Input-only streams */
126 #define SDW_SHIM2_PCMSCAP_OSS		GENMASK(7, 4)	/* Output-only streams */
129 /* Read-only PCM Stream Channel Count, y variable is stream */
138 #define SDW_SHIM2_PCMSYCHM_DIR		BIT(15)		/* HDaudio stream direction */
140 /* SHIM2 vendor-specific registers */
142 #define SDW_SHIM2_INTEL_VS_LVSCTL_FCG	BIT(26)
144 #define SDW_SHIM2_INTEL_VS_LVSCTL_DCGD	BIT(30)
145 #define SDW_SHIM2_INTEL_VS_LVSCTL_ICGD	BIT(31)
154 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWE	BIT(0)
157 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWS	BIT(0)
160 #define SDW_SHIM2_INTEL_VS_IOCTL_MIF	BIT(0)
161 #define SDW_SHIM2_INTEL_VS_IOCTL_CO	BIT(1)
162 #define SDW_SHIM2_INTEL_VS_IOCTL_COE	BIT(2)
163 #define SDW_SHIM2_INTEL_VS_IOCTL_DO	BIT(3)
164 #define SDW_SHIM2_INTEL_VS_IOCTL_DOE	BIT(4)
165 #define SDW_SHIM2_INTEL_VS_IOCTL_BKE	BIT(5)
166 #define SDW_SHIM2_INTEL_VS_IOCTL_WPDD	BIT(6)
167 #define SDW_SHIM2_INTEL_VS_IOCTL_ODC	BIT(7)
168 #define SDW_SHIM2_INTEL_VS_IOCTL_CIBD	BIT(8)
169 #define SDW_SHIM2_INTEL_VS_IOCTL_DIBD	BIT(9)
170 #define SDW_SHIM2_INTEL_VS_IOCTL_HAMIFD	BIT(10)
173 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE	BIT(0)
174 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODS		BIT(1)
175 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE	BIT(2)
177 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE	BIT(5)
216  * struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables
218  * @count: link count found with "sdw-master-count" property
219  * @link_mask: bit-wise mask listing links enabled by BIOS menu
233 /* Intel clock-stop/pm_runtime quirk definitions */
240 #define SDW_INTEL_CLK_STOP_NOT_ALLOWED		BIT(0)
244  * reset and re-enumeration will be performed when the bus
246  * in-band wakes.
248 #define SDW_INTEL_CLK_STOP_TEARDOWN		BIT(1)
252  * (e.g. speaker amplifiers). The clock-stop mode is typically
253  * slightly higher power than when the IP is completely powered-off.
255 #define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY	BIT(2)
258  * Require a bus reset (and complete re-enumeration) when exiting
265 #define SDW_INTEL_CLK_STOP_BUS_RESET		BIT(3)
270  * struct sdw_intel_ctx - context allocated by the controller
275  * @link_mask: bit-wise mask listing SoundWire links reported by the
279  * @ldev: information for each link (controller-specific and kept
305  * struct sdw_intel_res - Soundwire Intel global resource structure,
316  * @link_mask: bit-wise mask listing links selected by the DSP driver
318  * machine-specific quirks are handled in the DSP driver.
325  * @eml_lock: mutex protecting shared registers in the HDaudio multi-link
372 #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE      BIT(1)
376 /* struct intel_sdw_hw_ops - SoundWire ops for Intel platforms.
385  * @link_power_up: power-up using chip-specific helpers
386  * @link_power_down: power-down with chip-specific helpers
388  * @shim_wake: enable/disable in-band wake management
391  * @sync_arm: helper for multi-link synchronization
392  * @sync_go_unlocked: helper for multi-link synchronization -
394  * @sync_go: helper for multi-link synchronization
395  * @sync_check_cmdsync_unlocked: helper for multi-link synchronization
396  * and bank switch - shim_lock is assumed to be locked at higher level
433  * and 6 system-unique Device Numbers for wake-capable devices.