| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | mediatek,syscon.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,syscon.yaml#
7 title: MediaTek Clock controller syscon's
14 The MediaTek clock controller syscon's provide various clocks to the system.
21 - mediatek,mt2701-bdpsys
22 - mediatek,mt2701-imgsys
23 - mediatek,mt2701-vdecsys
24 - mediatek,mt2712-bdpsys
25 - mediatek,mt2712-imgsys
26 - mediatek,mt2712-jpgdecsys
27 - mediatek,mt2712-mcucfg
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| H A D | mediatek,mt8188-clock.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8188
10 - Garmin Chang <garmin.chang@mediatek.com>
13 The clock architecture in MediaTek like below
25 - mediatek,mt8188-adsp-audio26m
26 - mediatek,mt8188-camsys
27 - mediatek,mt8188-camsys-rawa
28 - mediatek,mt8188-camsys-rawb
29 - mediatek,mt8188-camsys-yuva
30 - mediatek,mt8188-camsys-yuvb
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| H A D | mediatek,mt8195-clock.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8195
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The clock architecture in Mediatek like below
27 - mediatek,mt8195-scp_adsp
28 - mediatek,mt8195-imp_iic_wrap_s
29 - mediatek,mt8195-imp_iic_wrap_w
30 - mediatek,mt8195-mfgcfg
31 - mediatek,mt8195-wpesys
32 - mediatek,mt8195-wpesys_vpp0
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| H A D | mediatek,mt8192-clock.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8192
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The Mediatek functional clock controller provides various clocks on MT8192.
19 - mediatek,mt8192-scp_adsp
20 - mediatek,mt8192-imp_iic_wrap_c
21 - mediatek,mt8192-imp_iic_wrap_e
22 - mediatek,mt8192-imp_iic_wrap_s
23 - mediatek,mt8192-imp_iic_wrap_ws
24 - mediatek,mt8192-imp_iic_wrap_w
[all …]
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| H A D | mediatek,infracfg.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,infracfg.yaml#
7 title: MediaTek Infrastructure System Configuration Controller
13 The Mediatek infracfg controller provides various clocks and reset outputs
15 and <dt-bindings/clock/mediatek,mt*-infracfg.h>, and reset values in
17 <dt-bindings/reset/mediatek,mt*-infracfg.h>.
24 - mediatek,mt2701-infracfg
25 - mediatek,mt2712-infracfg
26 - mediatek,mt6735-infracfg
27 - mediatek,mt6765-infracfg
28 - mediatek,mt6795-infracfg
[all …]
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| H A D | mediatek,topckgen.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#
7 title: MediaTek Top Clock Generator Controller
14 The Mediatek topckgen controller provides various clocks to the system.
16 <dt-bindings/clock/mediatek,mt*-topckgen.h>.
22 - mediatek,mt6797-topckgen
23 - mediatek,mt7622-topckgen
24 - mediatek,mt8135-topckgen
25 - mediatek,mt8173-topckgen
26 - mediatek,mt8516-topckgen
28 - const: mediatek,mt7623-topckgen
[all …]
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| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | mediatek.yaml | 4 $id: http://devicetree.org/schemas/arm/mediatek.yaml#
7 title: MediaTek SoC based Platforms
10 - Sean Wang <sean.wang@mediatek.com>
13 Boards with a MediaTek SoC shall have the following properties.
23 - mediatek,mt2701-evb
24 - const: mediatek,mt2701
28 - mediatek,mt2712-evb
29 - const: mediatek,mt2712
34 - const: mediatek,mt6572
37 - mediatek,mt6580-evbp1
[all …]
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| /linux/Documentation/devicetree/bindings/iommu/ |
| H A D | mediatek,iommu.yaml | 4 $id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
7 title: MediaTek IOMMU Architecture Implementation
10 - Yong Wu <yong.wu@mediatek.com>
13 Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
73 - mediatek,mt2701-m4u # generation one
74 - mediatek,mt2712-m4u # generation two
75 - mediatek,mt6779-m4u # generation two
76 - mediatek,mt6795-m4u # generation two
77 - mediatek,mt6893-iommu-mm # generation two
78 - mediatek,mt8167-m4u # generation two
[all …]
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| /linux/Documentation/devicetree/bindings/serial/ |
| H A D | mediatek,uart.yaml | 4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
26 - mediatek,mt2701-uart
27 - mediatek,mt2712-uart
28 - mediatek,mt6572-uart
29 - mediatek,mt6580-uart
30 - mediatek,mt6582-uart
31 - mediatek,mt6589-uart
[all …]
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| /linux/arch/arm/boot/dts/mediatek/ |
| H A D | mt7623n.dtsi | 3 * Copyright © 2017-2020 MediaTek Inc.
4 * Author: Sean Wang <sean.wang@mediatek.com>
5 * Ryder Lee <ryder.lee@mediatek.com>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
52 compatible = "mediatek,mt7623-mmsys",
53 "mediatek,mt2701-mmsys",
60 compatible = "mediatek,mt7623-smi-larb",
61 "mediatek,mt2701-smi-larb";
[all …]
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | mtk-sd.yaml | 10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
20 - mediatek,mt6795-mmc
21 - mediatek,mt7620-mmc
22 - mediatek,mt7622-mmc
23 - mediatek,mt7986-mmc
24 - mediatek,mt7988-mmc
[all …]
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | mediatek,smi-larb.yaml | 2 # Copyright (c) 2020 MediaTek Inc.
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
14 The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
20 - mediatek,mt2701-smi-larb
21 - mediatek,mt2712-smi-larb
22 - mediatek,mt6779-smi-larb
23 - mediatek,mt6795-smi-larb
24 - mediatek,mt6893-smi-larb
25 - mediatek,mt8167-smi-larb
[all …]
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| H A D | mediatek,smi-common.yaml | 2 # Copyright (c) 2020 MediaTek Inc.
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
14 The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
16 MediaTek SMI have two generations of HW architecture, here is the list
32 - mediatek,mt2701-smi-common
33 - mediatek,mt2712-smi-common
34 - mediatek,mt6779-smi-common
35 - mediatek,mt6795-smi-common
36 - mediatek,mt6893-smi-common
[all …]
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | mediatek,spi-mt65xx.yaml | 4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
7 title: SPI Bus controller for MediaTek ARM SoCs
10 - Leilk Liu <leilk.liu@mediatek.com>
20 - mediatek,mt7629-spi
21 - mediatek,mt8365-spi
22 - const: mediatek,mt7622-spi
25 - mediatek,mt8516-spi
26 - const: mediatek,mt2712-spi
29 - mediatek,mt6779-spi
30 - mediatek,mt8186-spi
[all …]
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | mediatek,mt6577-sysirq.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mediatek,mt6577-sysirq.yaml#
7 title: MediaTek sysirq
10 MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
19 - const: mediatek,mt6577-sysirq
22 - mediatek,mt2701-sysirq
23 - mediatek,mt2712-sysirq
24 - mediatek,mt6572-sysirq
25 - mediatek,mt6580-sysirq
26 - mediatek,mt6582-sysirq
27 - mediatek,mt6589-sysirq
[all …]
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| /linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | mediatek,mtk-wdt.yaml | 4 $id: http://devicetree.org/schemas/watchdog/mediatek,mtk-wdt.yaml#
7 title: MediaTek SoCs Watchdog timer
23 - mediatek,mt2712-wdt
24 - mediatek,mt6589-wdt
25 - mediatek,mt6735-wdt
26 - mediatek,mt6795-wdt
27 - mediatek,mt7986-wdt
28 - mediatek,mt7988-wdt
29 - mediatek,mt8183-wdt
30 - mediatek,mt8186-wdt
[all …]
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| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | mediatek,timer.yaml | 4 $id: http://devicetree.org/schemas/timer/mediatek,timer.yaml#
7 title: MediaTek SoC timers
13 MediaTek SoCs have different timers on different platforms,
22 - mediatek,mt6577-timer
23 - mediatek,mt6765-timer
24 - mediatek,mt6795-systimer
28 - mediatek,mt2701-timer
29 - mediatek,mt6572-timer
30 - mediatek,mt6580-timer
31 - mediatek,mt6582-timer
[all …]
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| /linux/drivers/pinctrl/mediatek/ |
| H A D | Kconfig | 2 menu "MediaTek pinctrl drivers"
6 tristate "MediaTek External Interrupt Support"
51 bool "MediaTek MT7620 pin control"
58 bool "MediaTek MT7621 pin control"
65 bool "MediaTek MT76X8 pin control"
94 bool "MediaTek MT2701 pin control"
101 bool "MediaTek MT7623 pin control with generic binding"
108 bool "MediaTek MT7629 pin control"
115 bool "MediaTek MT8135 pin control"
122 bool "MediaTek MT8127 pin control"
[all …]
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | mediatek,net.yaml | 4 $id: http://devicetree.org/schemas/net/mediatek,net.yaml#
7 title: MediaTek Frame Engine Ethernet controller
14 The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
25 - mediatek,mt7981-eth
26 - mediatek,mt7986-eth
[all …]
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| /linux/Documentation/devicetree/bindings/arm/mediatek/ |
| H A D | mediatek,mmsys.yaml | 4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#
7 title: MediaTek mmsys controller
13 The MediaTek mmsys system controller provides clock control, routing control,
24 - mediatek,mt2701-mmsys
25 - mediatek,mt2712-mmsys
26 - mediatek,mt6765-mmsys
27 - mediatek,mt6779-mmsys
28 - mediatek,mt6795-mmsys
29 - mediatek,mt6797-mmsys
30 - mediatek,mt8167-mmsys
[all …]
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8188.dtsi | 3 * Copyright (c) 2023 MediaTek Inc.
8 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
12 #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
14 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
15 #include <dt-bindings/power/mediatek,mt8188-power.h>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
21 compatible = "mediatek,mt8188";
467 mediatek,platform = <&afe>;
933 compatible = "mediatek,cpufreq-hw";
[all …]
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| H A D | mt6795.dtsi | 3 * Copyright (c) 2015 MediaTek Inc.
5 * Authors: Mars.C <mars.cheng@mediatek.com>
11 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
12 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
16 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
19 compatible = "mediatek,mt6795";
270 compatible = "mediatek,mt6795-topckgen", "syscon";
276 compatible = "mediatek,mt6795-infracfg", "syscon";
283 compatible = "mediatek,mt6795-pericfg", "syscon";
290 compatible = "mediatek,mt6795-scpsys", "syscon", "simple-mfd";
[all …]
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| H A D | mt8195.dtsi | 3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
21 compatible = "mediatek,mt8195";
328 mediatek,platform = <&afe>;
356 compatible = "mediatek,cpufreq-hw";
486 compatible = "mediatek,mt8195-topckgen", "syscon";
492 compatible = "mediatek,mt8195-infracfg_ao", "syscon";
499 compatible = "mediatek,mt8195-pericfg", "syscon";
505 compatible = "mediatek,mt8195-pinctrl";
[all …]
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| /linux/Documentation/devicetree/bindings/nvmem/ |
| H A D | mediatek,efuse.yaml | 4 $id: http://devicetree.org/schemas/nvmem/mediatek,efuse.yaml#
7 title: MediaTek efuse
10 MediaTek's efuse is used for storing calibration data, it can be accessed
14 - Andrew-CT Chen <andrew-ct.chen@mediatek.com>
15 - Lala Lin <lala.lin@mediatek.com>
29 - mediatek,mt8188-efuse
30 - mediatek,mt8189-efuse
31 - mediatek,mt8196-efuse
32 - const: mediatek,mt8186-efuse
33 - const: mediatek,mt8186-efuse
[all …]
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| /linux/Documentation/devicetree/bindings/soc/mediatek/ |
| H A D | mediatek,mutex.yaml | 4 $id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
7 title: Mediatek mutex
14 Mediatek mutex, namely MUTEX, is used to send the triggers signals called
21 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
27 - mediatek,mt2701-disp-mutex
28 - mediatek,mt2712-disp-mutex
29 - mediatek,mt6795-disp-mutex
30 - mediatek,mt8167-disp-mutex
31 - mediatek,mt8173-disp-mutex
32 - mediatek,mt8183-disp-mutex
[all …]
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