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48 #define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */422 #define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */430 #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */431 #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */441 #define PCI_X_SSTATUS_133MHZ 0x0002 /* 133 MHz capable */446 #define PCI_X_SSTATUS_266MHZ 0x4000 /* 266 MHz capable */447 #define PCI_X_SSTATUS_533MHZ 0x8000 /* 533 MHz capable */