| /qemu/docs/specs/ |
| H A D | vmw_pvscsi-spec.rst | 18 The registers area is used to raise hypervisor interrupts and issue device
30 issue device interrupts, and control interrupt masking.
50 PVSCSI Device to Host Interrupts
55 Completion interrupts (completion ring notifications):
60 Message interrupts (message ring notifications):
65 Interrupts are controlled via the ``PVSCSI_REG_OFFSET_INTR_MASK``
70 In the case of legacy interrupts, the ``PVSCSI_REG_OFFSET_INTR_STATUS``
71 register is used to check which interrupt has arrived. Interrupts are
90 f. Unmask completion and message (if device messages enabled) interrupts
95 a. Mask interrupts
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| H A D | ivshmem-spec.rst | 43 kernel driver to handle interrupts. Requires the device to be
44 configured for interrupts, obviously.
47 configured for interrupts. It becomes safely accessible only after
54 it is configured for interrupts.
89 IVPosition Register: if the device is not configured for interrupts,
96 configured for interrupts. A positive IVPosition means interrupts,
103 If the device is not configured for interrupts, the write is ignored.
107 complete. Interrupts can regress to this state on migration.
130 When configured for interrupts, the peers share eventfd objects in
146 (these contain file descriptors for sending interrupts),
[all …]
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| /qemu/pc-bios/dtb/ |
| H A D | canyonlands.dts | 70 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
82 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
94 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
124 interrupts = <11 1>;
143 interrupts = <0x1d 0x4>;
159 interrupts = < /*TXEOB*/ 0x6 0x4
169 interrupts = <0x1d 4>;
177 interrupts = <0x1e 4>;
187 interrupts = <0x0 0x1 0x2>;
197 interrupts = <0x5 0x4>;
[all …]
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| H A D | bamboo.dts | 97 interrupts = <7 4>;
106 interrupts = <5 1>;
118 interrupts = <0 4>;
129 interrupts = <1 4>;
137 interrupts = <2 4>;
145 interrupts = <7 4>;
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| /qemu/tests/functional/ |
| H A D | test_x86_64_kvm_xen.py | 88 'grep xen-pirq.*msi /proc/interrupts',
98 'grep xen-pirq.* /proc/interrupts',
108 'grep xen-pirq /proc/interrupts',
118 'grep xen-pirq /proc/interrupts',
122 'grep PCI-MSI /proc/interrupts',
132 'grep xen-platform-pci /proc/interrupts',
143 'grep xen-platform-pci /proc/interrupts',
153 'grep xen-platform-pci /proc/interrupts',
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| H A D | test_mips_malta.py | 20 'grep XT-PIC /proc/interrupts',
24 'grep XT-PIC /proc/interrupts',
28 'grep XT-PIC /proc/interrupts',
32 'grep XT-PIC /proc/interrupts',
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| /qemu/hw/intc/ |
| H A D | arm_gicv3.c | 14 * the device class itself and the functions for handling interrupts
45 /* If multiple pending interrupts have the same priority then it is an in irqbetter()
57 /* Recalculate which distributor interrupts are actually pending in gicd_int_pending()
58 * in the group of 32 interrupts starting at irq (which should be a multiple in gicd_int_pending()
103 /* Recalculate which redistributor interrupts are actually pending, in gicr_int_pending()
181 * redistributor interrupts (SGIs and PPIs). in gicv3_redist_update_noirqset()
189 /* Find out which redistributor interrupts are eligible to be in gicv3_redist_update_noirqset()
254 * changed affecting @len interrupts starting at @start,
285 /* Interrupts targeting no implemented CPU should remain pending in gicv3_update_noirqset()
376 * [0..N-1] : external interrupts in gicv3_set_irq()
[all …]
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| H A D | vgic_common.h | 28 * [0..N-1] : external interrupts
29 * [N..N+31] : PPI (internal) interrupts for CPU 0
30 * [N+32..N+63] : PPI (internal interrupts for CPU 1
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| H A D | arm_gicv3_dist.c | 19 * Secure interrupts:
20 * 0b00: no access (NS accesses to bits for Secure interrupts will RAZ/WI)
29 * word for this set of interrupts to give an overall mask.
63 * interrupts; each bit is 1 if access is permitted by the in mask_group_and_nsacr()
69 /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI in mask_group_and_nsacr()
101 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. in gicd_write_bitmap_reg()
124 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. in gicd_write_set_bitmap_reg()
148 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. in gicd_write_clear_bitmap_reg()
172 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. in gicd_read_bitmap_reg()
185 * interrupts, the PENDING state is the logical OR of the state of in gicd_read_bitmap_reg()
[all …]
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| /qemu/include/exec/ |
| H A D | cpu-interrupt.h | 19 * This is typically used for interrupts from devices.
39 * Several target-specific external hardware interrupts. Each target/cpu.h
49 * Several target-specific internal interrupts. These differ from the
50 * preceding target-specific interrupts in that they are intended to
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| /qemu/pc-bios/s390-ccw/ |
| H A D | start.S | 68 /* enable service interrupts in cr0 */
88 /* enable I/O interrupts in cr6 */
102 /* disable service interrupts in cr0 */
109 /* disable I/O interrupts in cr6 */
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| /qemu/tests/qtest/libqos/ |
| H A D | ahci.c | 48 uint32_t interrupts; /* Expected interrupts for this command. */ member
89 uint32_t interrupts; member
306 /* Verify Interrupts Cleared */ in ahci_hba_enable()
316 /* Enable All Interrupts: */ in ahci_hba_enable()
358 * and clear the initial interrupts might be good. */ in ahci_hba_enable()
389 * Clear a port's interrupts and status information prior to a test.
395 /* Clear out this port's interrupts (ignore the init register d2h fis) */ in ahci_port_clear()
419 reg &= ~cmd->interrupts; in ahci_port_check_error()
471 * and clear expected interrupts. */ in ahci_port_check_interrupts()
476 /* Check for expected interrupts */ in ahci_port_check_interrupts()
[all …]
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| /qemu/include/hw/xen/interface/hvm/ |
| H A D | params.h | 183 * interrupts that have been missed due to preemption. Deliver missed
184 * interrupts when the vcpu is rescheduled and advance the vcpu's virtual
187 * As above, missed interrupts are delivered, but guest time always tracks
190 * No missed interrupts are held pending. Instead, to ensure ticks are
195 * Missed interrupts are collapsed together and delivered as one 'late tick'.
216 /* Boolean: Enable aligning all periodic vpts to reduce interrupts */
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| /qemu/hw/display/ |
| H A D | omap_lcdc.c | 40 int interrupts; member
55 if (s->frame_done && (s->interrupts & 1)) { in omap_lcd_interrupts()
60 if (s->palette_done && (s->interrupts & 2)) { in omap_lcd_interrupts()
287 if (omap_lcd->dma->interrupts & 1) in omap_update_display()
361 if (s->dma->interrupts & (1 << 1)) in omap_lcd_update()
386 (s->tft << 7) | (s->interrupts << 3) | in omap_lcdc_read()
420 s->interrupts = (value >> 3) & 3; in omap_lcdc_write()
470 s->interrupts = 0; in omap_lcdc_reset()
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| /qemu/hw/dma/ |
| H A D | omap_dma.c | 57 int interrupts; member
126 /* Interrupts */
305 /* First three interrupts are shared between two channels each. */ in omap_dma_interrupts_3_1_update()
414 if (ch->interrupts & LAST_FRAME_INTR) in omap_dma_transfer_generic()
420 if (ch->interrupts & HALF_FRAME_INTR) in omap_dma_transfer_generic()
430 if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync) in omap_dma_transfer_generic()
455 if (ch->interrupts & END_FRAME_INTR) in omap_dma_transfer_generic()
478 if (ch->interrupts & END_BLOCK_INTR) in omap_dma_transfer_generic()
516 if (ch->interrupts & TIMEOUT_INTR)
549 (ch->interrupts & LAST_FRAME_INTR) &&
[all …]
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| /qemu/target/xtensa/core-dc232b/ |
| H A D | core-isa.h | 179 INTERRUPTS and TIMERS
183 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
187 #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
189 #define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
195 /* Masks of interrupts at each interrupt level: */
204 /* Masks of interrupts at each range 1..n of interrupt levels: */
265 /* Masks of interrupts for each type of interrupt: */
286 /* (There are many interrupts each at level(s) 1, 3.) */
293 * map to external BInterrupt<n> pins, for those interrupts
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| /qemu/target/xtensa/core-fsf/ |
| H A D | core-isa.h | 175 INTERRUPTS and TIMERS
179 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
183 #define XCHAL_NUM_INTERRUPTS 17 /* number of interrupts */
185 #define XCHAL_NUM_EXTINTERRUPTS 10 /* num of external interrupts */
191 /* Masks of interrupts at each interrupt level: */
200 /* Masks of interrupts at each range 1..n of interrupt levels: */
249 /* Masks of interrupts for each type of interrupt: */
265 /* (There are many interrupts each at level(s) 1, 2, 3.) */
272 * map to external BInterrupt<n> pins, for those interrupts
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| /qemu/hw/riscv/ |
| H A D | sifive_u.c | 217 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", in create_fdt()
273 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", in create_fdt()
299 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, in create_fdt()
319 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", in create_fdt()
337 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", in create_fdt()
356 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ); in create_fdt()
381 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ); in create_fdt()
415 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); in create_fdt()
445 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", in create_fdt()
461 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", in create_fdt()
[all …]
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| /qemu/hw/arm/ |
| H A D | xlnx-versal-virt.c | 131 qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts", in fdt_add_gic_nodes()
151 qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts", in fdt_add_timer_nodes()
193 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", in fdt_add_usb_xhci_nodes()
227 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", in fdt_add_uart_nodes()
264 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", in fdt_add_canfd_nodes()
309 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", in fdt_add_gem_nodes()
341 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", in fdt_add_zdma_nodes()
367 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", in fdt_add_sd_nodes()
385 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", in fdt_add_rtc_node()
406 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", in fdt_add_bbram_node()
[all …]
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| /qemu/include/hw/intc/ |
| H A D | exynos4210_combiner.h | 33 uint8_t src_pending; /* Pending source interrupts before masking */
39 /* Number of groups and total number of interrupts for the internal combiner */
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| /qemu/target/xtensa/core-dsp3400/ |
| H A D | core-isa.h | 246 INTERRUPTS and TIMERS
250 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
254 #define XCHAL_NUM_INTERRUPTS 13 /* number of interrupts */
256 #define XCHAL_NUM_EXTINTERRUPTS 9 /* num of external interrupts */
262 /* Masks of interrupts at each interrupt level: */
271 /* Masks of interrupts at each range 1..n of interrupt levels: */
312 /* Masks of interrupts for each type of interrupt: */
329 /* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
336 * map to external BInterrupt<n> pins, for those interrupts
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| /qemu/target/xtensa/core-lx106/ |
| H A D | core-isa.h | 259 INTERRUPTS and TIMERS
263 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
267 #define XCHAL_NUM_INTERRUPTS 15 /* number of interrupts */
269 #define XCHAL_NUM_EXTINTERRUPTS 13 /* num of external interrupts */
275 /* Masks of interrupts at each interrupt level: */
284 /* Masks of interrupts at each range 1..n of interrupt levels: */
331 /* Masks of interrupts for each type of interrupt: */
349 /* (There are many interrupts each at level(s) 1.) */
356 * map to external BInterrupt<n> pins, for those interrupts
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| /qemu/target/xtensa/core-dc233c/ |
| H A D | core-isa.h | 227 INTERRUPTS and TIMERS
231 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
235 #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
237 #define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
243 /* Masks of interrupts at each interrupt level: */
252 /* Masks of interrupts at each range 1..n of interrupt levels: */
313 /* Masks of interrupts for each type of interrupt: */
334 /* (There are many interrupts each at level(s) 1, 3.) */
341 * map to external BInterrupt<n> pins, for those interrupts
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| /qemu/docs/system/devices/ |
| H A D | ivshmem-flat.rst | 13 notification via HW interrupts and Inter-VM shared memory. This allows the
25 Although the ivshmem-flat supports both peer notification (interrupts) and
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| /qemu/include/hw/arm/ |
| H A D | armsse.h | 44 * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
45 * (In hardware, the SSE-200 permits the number of expansion interrupts
62 * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
64 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
|