Searched full:interconnect (Results 1 – 11 of 11) sorted by relevance
| /qemu/pc-bios/dtb/ |
| H A D | petalogix-ml605.dts | 97 xlnx,interconnect = < 0x02 >;
114 xlnx,stream-interconnect = < 0x00 >;
137 compatible = "xlnx,axi-interconnect-1.02.a\0simple-bus";
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| H A D | petalogix-s3adsp1800.dts | 78 xlnx,interconnect = <0x01>;
250 xlnx,interconnect = <0x01>;
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| /qemu/include/exec/ |
| H A D | memattrs.h | 40 * Bus interconnect and peripherals can access anything (memories,
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| /qemu/docs/system/arm/ |
| H A D | vexpress.rst | 35 - PL301 AXI interconnect
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| /qemu/hw/arm/ |
| H A D | xilinx_zynq.c | 442 /* AMBA Network Interconnect Advanced Quality of Service (QoS-301) */ in zynq_init()
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| H A D | vexpress.c | 388 /* 0x2a000000: PL301 AXI interconnect: not modelled */ in a15_daughterboard_init()
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| H A D | fsl-imx8mp.c | 100 [FSL_IMX8MP_INTERCONNECT] = { 0x32700000, 1 * MiB, "interconnect" },
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| /qemu/docs/system/devices/ |
| H A D | cxl.rst | 3 From the view of a single host, CXL is an interconnect standard that
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| /qemu/include/block/ |
| H A D | ufs.h | 1014 /* Interconnect descriptor parameters offsets in bytes*/
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| /qemu/tests/qtest/ |
| H A D | ufs-test.c | 965 /* Read Interconnect Descriptor */ in ufstest_query_desc_request()
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| /qemu/tests/functional/acpi-bits/bits-tests/ |
| H A D | smbios.py2 | 248 0xD: 'Interconnect Board'
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