| /linux-5.10/Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra20-i2c.txt | 1 NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
4 - compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
5 "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
6 For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
7 "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
9 Details of compatible are as follows:
10 nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
11 controller. This only support master mode of I2C communication. Register
12 interface/offset and interrupts handling are different than generic I2C
13 controller. Driver of DVC I2C controller is only compatible with
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| D | st,stm32-i2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: I2C controller embedded in STMicroelectronics STM32 I2C platform
10 - Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
16 compatible:
19 - st,stm32f7-i2c
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| D | marvell,mv64xxx-i2c.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/marvell,mv64xxx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MV64XXX I2C Controller Device Tree Bindings
10 - Gregory CLEMENT <gregory.clement@bootlin.com>
13 compatible:
15 - const: allwinner,sun4i-a10-i2c
16 - items:
17 - const: allwinner,sun7i-a20-i2c
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| D | snps,designware-i2c.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB I2C Controller
10 - Jarkko Nikula <jarkko.nikula@linux.intel.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
16 compatible:
19 const: mscc,ocelot-i2c
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| D | renesas,i2c.txt | 1 I2C for R-Car platforms
4 - compatible:
5 "renesas,i2c-r8a7742" if the device is a part of a R8A7742 SoC.
6 "renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC.
7 "renesas,i2c-r8a7744" if the device is a part of a R8A7744 SoC.
8 "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC.
9 "renesas,i2c-r8a77470" if the device is a part of a R8A77470 SoC.
10 "renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC.
11 "renesas,i2c-r8a774b1" if the device is a part of a R8A774B1 SoC.
12 "renesas,i2c-r8a774c0" if the device is a part of a R8A774C0 SoC.
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| D | amlogic,meson6-i2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/i2c/amlogic,meson6-i2c.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson I2C Controller
11 - Neil Armstrong <narmstrong@baylibre.com>
12 - Beniamino Galvani <b.galvani@gmail.com>
15 - $ref: /schemas/i2c/i2c-controller.yaml#
18 compatible:
20 - amlogic,meson6-i2c # Meson6, Meson8 and compatible SoCs
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| D | i2c-mpc.txt | 1 * I2C
5 - reg : Offset and length of the register set for the device
6 - compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a
7 compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121,
9 "fsl,mpc5121-i2c-ctrl" is required as shown in the example below.
13 - interrupts : <a b> where a is the interrupt number and b is a
18 - fsl,preserve-clocking : boolean; if defined, the clock settings
20 - clock-frequency : desired I2C bus clock frequency in Hz.
21 - fsl,timeout : I2C bus timeout in microseconds.
26 i2c@1740 {
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| D | brcm,brcmstb-i2c.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/brcm,brcmstb-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kamal Dasu <kdasu.kdev@gmail.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
16 compatible:
18 - brcm,bcm2711-hdmi-i2c
19 - brcm,brcmstb-i2c
20 - brcm,brcmper-i2c
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| D | i2c-at91.txt | 1 I2C for Atmel platforms
4 - compatible : Must be one of:
5 "atmel,at91rm9200-i2c",
6 "atmel,at91sam9261-i2c",
7 "atmel,at91sam9260-i2c",
8 "atmel,at91sam9g20-i2c",
9 "atmel,at91sam9g10-i2c",
10 "atmel,at91sam9x5-i2c",
11 "atmel,sama5d4-i2c",
12 "atmel,sama5d2-i2c",
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| D | i2c-s3c2410.txt | 1 * Samsung's I2C controller
3 The Samsung's I2C controller is used to interface with I2C devices.
6 - compatible: value should be either of the following.
7 (a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c.
8 (b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c.
9 (c) "samsung, s3c2440-hdmiphy-i2c", for s3c2440-like i2c used
11 (d) "samsung, exynos5-sata-phy-i2c", for s3c2440-like i2c used as
13 - reg: physical base address of the controller and length of memory mapped
15 - interrupts: interrupt number to the cpu.
16 - samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges.
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| D | i2c-demux-pinctrl.txt | 1 Pinctrl-based I2C Bus DeMux
3 This binding describes an I2C bus demultiplexer that uses pin multiplexing to
4 route the I2C signals, and represents the pin multiplexing configuration using
5 the pinctrl device tree bindings. This may be used to select one I2C IP core at
6 runtime which may have a better feature set for a given task than another I2C
10 +-------------------------------+
12 | | +-----+ +-----+
13 | +------------+ | | dev | | dev |
14 | |I2C IP Core1|--\ | +-----+ +-----+
15 | +------------+ \-------+ | | |
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| /linux-5.10/Documentation/devicetree/bindings/ |
| D | unittest.txt | 6 - compatible: must be "unittest"
12 compatible = "unittest";
15 2) OF unittest i2c adapter platform device
20 - compatible: must be unittest-i2c-bus
22 Children nodes contain unittest i2c devices.
25 unittest-i2c-bus {
26 compatible = "unittest-i2c-bus";
29 3) OF unittest i2c device
31 ** I2C unittest device
34 - compatible: must be unittest-i2c-dev
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| /linux-5.10/arch/arm64/boot/dts/mediatek/ |
| D | mt6797.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
13 compatible = "mediatek,mt6797";
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
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| /linux-5.10/arch/arm/boot/dts/ |
| D | ibm-power9-dual.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
7 #address-cells = <1>;
8 #size-cells = <1>;
9 chip-id = <0>;
12 compatible = "ibm,fsi2pib";
16 i2c@1800 {
17 compatible = "ibm,fsi-i2c-master";
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cfam0_i2c0: i2c-bus@0 {
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| D | aspeed-bmc-facebook-tiogapass.dts | 1 // SPDX-License-Identifier: GPL-2.0+
4 /dts-v1/;
6 #include "aspeed-g5.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
8 #include <dt-bindings/i2c/i2c.h>
12 compatible = "facebook,tiogapass-bmc", "aspeed,ast2500";
18 * Hardcode the bus number of i2c switches' channels to
39 stdout-path = &uart5;
47 iio-hwmon {
48 compatible = "iio-hwmon";
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| D | aspeed-bmc-quanta-q71l.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3 #include "aspeed-g4.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
8 compatible = "quanta,q71l-bmc", "aspeed,ast2400";
30 stdout-path = &uart5;
38 reserved-memory {
39 #address-cells = <1>;
40 #size-cells = <1>;
44 no-map;
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| D | aspeed-bmc-opp-mihawk.dts | 1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
3 #include "aspeed-g5.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
5 #include <dt-bindings/leds/leds-pca955x.h>
9 compatible = "ibm,mihawk-bmc", "aspeed,ast2500";
59 stdout-path = &uart5;
67 reserved-memory {
68 #address-cells = <1>;
69 #size-cells = <1>;
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| D | aspeed-bmc-opp-tacoma.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /dts-v1/;
5 #include "aspeed-g6.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
7 #include <dt-bindings/i2c/i2c.h>
8 #include <dt-bindings/leds/leds-pca955x.h>
12 compatible = "ibm,tacoma-bmc", "aspeed,ast2600";
15 stdout-path = &uart5;
24 reserved-memory {
25 #address-cells = <1>;
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| D | r8a7790-lager.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
7 * Copyright (C) 2015-2016 Renesas Electronics Corporation
11 * SSI-AK4643
38 /dts-v1/;
40 #include <dt-bindings/gpio/gpio.h>
41 #include <dt-bindings/input/input.h>
45 compatible = "renesas,lager", "renesas,r8a7790";
60 stdout-path = "serial0:115200n8";
74 #address-cells = <1>;
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| D | aspeed-g6.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
6 #include <dt-bindings/clock/ast2600-clock.h>
10 compatible = "aspeed,ast2600";
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
43 #address-cells = <1>;
44 #size-cells = <0>;
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| /linux-5.10/drivers/mfd/ |
| D | stmpe-i2c.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ST Microelectronics MFD: stmpe's i2c client specific driver
5 * Copyright (C) ST-Ericsson SA 2010
8 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
12 #include <linux/i2c.h>
22 struct i2c_client *i2c = stmpe->client; in i2c_reg_read() local
24 return i2c_smbus_read_byte_data(i2c, reg); in i2c_reg_read()
29 struct i2c_client *i2c = stmpe->client; in i2c_reg_write() local
31 return i2c_smbus_write_byte_data(i2c, reg, val); in i2c_reg_write()
36 struct i2c_client *i2c = stmpe->client; in i2c_block_read() local
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| D | axp20x-i2c.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * I2C driver for the X-Powers' Power Management ICs
5 * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
6 * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
9 * This driver supports the I2C variants.
18 #include <linux/i2c.h>
25 static int axp20x_i2c_probe(struct i2c_client *i2c, in axp20x_i2c_probe() argument
31 axp20x = devm_kzalloc(&i2c->dev, sizeof(*axp20x), GFP_KERNEL); in axp20x_i2c_probe()
33 return -ENOMEM; in axp20x_i2c_probe()
35 axp20x->dev = &i2c->dev; in axp20x_i2c_probe()
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| /linux-5.10/arch/arm64/boot/dts/toshiba/ |
| D | tmpv7708.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
16 compatible = "toshiba,tmpv7708";
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
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| /linux-5.10/drivers/of/unittest-data/ |
| D | tests-overlay.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 testcase-data {
5 overlay-node {
8 unittest_test_bus: test-bus {
9 compatible = "simple-bus";
10 #address-cells = <1>;
11 #size-cells = <0>;
13 unittest100: test-unittest100 {
14 compatible = "unittest";
19 unittest101: test-unittest101 {
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| /linux-5.10/arch/arm64/boot/dts/allwinner/ |
| D | sun50i-a100.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
8 #include <dt-bindings/clock/sun50i-a100-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-a100-ccu.h>
10 #include <dt-bindings/reset/sun50i-a100-r-ccu.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
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