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/linux-5.10/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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Dhifive-unleashed-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 #include "fu540-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
17 stdout-path = "serial0";
21 timebase-frequency = <RTCCLK_FREQ>;
33 #clock-cells = <0>;
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/linux-5.10/Documentation/devicetree/bindings/dma/
Dsifive,fu540-c000-pdma.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive Unleashed Rev C000 Platform DMA
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
28 - const: sifive,fu540-c000-pdma
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/linux-5.10/Documentation/devicetree/bindings/pwm/
Dpwm-sifive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yash Shah <yash.shah@sifive.com>
12 - Sagar Kadam <sagar.kadam@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
21 numbers can be found here -
23 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
28 - const: sifive,fu540-c000-pwm
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/linux-5.10/Documentation/devicetree/bindings/clock/sifive/
Dfu540-prci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 On the FU540 family of SoCs, most system-wide clock and reset integration
18 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
27 const: sifive,fu540-c000-prci
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/linux-5.10/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-sifive.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: "spi-controller.yaml#"
20 - const: sifive,fu540-c000-spi
21 - const: sifive,spi0
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/linux-5.10/Documentation/devicetree/bindings/riscv/
Dsifive-l2-cache.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Yash Shah <yash.shah@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
18 acts as directory-based coherency manager.
22 - $ref: /schemas/cache-controller.yaml#
28 - enum:
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Dsifive.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive SoC-based boards
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 SiFive SoC-based boards
21 - enum:
22 - sifive,hifive-unleashed-a00
23 - const: sifive,fu540-c000
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/linux-5.10/Documentation/devicetree/bindings/net/
Dmacb.txt4 - compatible: Should be "cdns,[<chip>-]{macb|gem}"
5 Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
6 Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs.
7 Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC.
8 Use "cdns,np4-macb" for NP4 SoC devices.
9 Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
10 Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on
12 Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs.
13 Use "atmel,sama5d3-macb" for the 10/100Mbit IP available on Atmel sama5d3 SoCs.
14 Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs.
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/linux-5.10/Documentation/devicetree/bindings/gpio/
Dsifive,gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yash Shah <yash.shah@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
16 - const: sifive,fu540-c000-gpio
17 - const: sifive,gpio0
28 interrupt-controller: true
30 "#interrupt-cells":
36 "#gpio-cells":
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/linux-5.10/Documentation/devicetree/bindings/serial/
Dsifive-serial.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: /schemas/serial.yaml#
20 - const: sifive,fu540-c000-uart
21 - const: sifive,uart0
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/linux-5.10/drivers/dma/sf-pdma/
Dsf-pdma.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SiFive FU540 Platform DMA driver
7 * - drivers/dma/fsl-edma.c
8 * - drivers/dma/dw-edma/
9 * - drivers/dma/pxa-dma.c
12 * - Chapter 12 "Platform DMA Engine (PDMA)" of
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
20 #include <linux/dma-direction.h>
23 #include "../virt-dma.h"
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Dsf-pdma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SiFive FU540 Platform DMA driver
7 * - drivers/dma/fsl-edma.c
8 * - drivers/dma/dw-edma/
9 * - drivers/dma/pxa-dma.c
12 * - Chapter 12 "Platform DMA Engine (PDMA)" of
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
21 #include <linux/dma-mapping.h>
25 #include "sf-pdma.h"
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/linux-5.10/Documentation/devicetree/bindings/sifive/
Dsifive-blocks-ip-versioning.txt1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
17 auto-discovery, the maintainers of these IP blocks intend to increment
25 upstream sifive-blocks commits. It is expected that most drivers will
26 match on these IP block-specific compatible strings.
29 continue to specify an SoC-specific compatible string value, such as
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/linux-5.10/Documentation/devicetree/bindings/i2c/
Di2c-ocores.txt1 Device tree configuration for i2c-ocores
4 - compatible : "opencores,i2c-ocores"
6 "sifive,fu540-c000-i2c", "sifive,i2c0"
8 FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
10 - reg : bus address start and address range size of device
11 - clocks : handle to the controller clock; see the note below.
12 Mutually exclusive with opencores,ip-clock-frequency
13 - opencores,ip-clock-frequency: frequency of the controller clock in Hz;
15 - #address-cells : should be <1>
16 - #size-cells : should be <0>
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/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
12 (PLIC) high-level specification in the RISC-V Privileged Architecture
17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
20 Each interrupt can be enabled on per-context basis. Any context can claim
28 While the PLIC supports both edge-triggered and level-triggered interrupts,
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Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
28 - #interrupt-cells : should be <1>. The interrupt sources are defined by the
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/linux-5.10/drivers/clk/sifive/
Dfu540-prci.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * The FU540 PRCI implements clock and reset control for the SiFive
17 * FU540-C000 chip. This driver assumes that it has sole control
21 * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
24 * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
27 #include <dt-bindings/clock/sifive-fu540-prci.h>
29 #include <linux/clk-provider.h>
30 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
139 * struct __prci_data - per-device-instance data
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/linux-5.10/drivers/clk/analogbits/
Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
28 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
36 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
39 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
68 * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
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/linux-5.10/drivers/i2c/busses/
Di2c-ocores.c1 // SPDX-License-Identifier: GPL-2.0
3 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
22 #include <linux/platform_data/i2c-ocores.h>
88 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
92 iowrite8(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_8()
97 iowrite16(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_16()
102 iowrite32(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_32()
107 iowrite16be(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_16be()
112 iowrite32be(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_32be()
117 return ioread8(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_8()
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/linux-5.10/drivers/soc/sifive/
Dsifive_l2_cache.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 SiFive, Inc.
53 return -EINVAL; in l2_write()
57 return -EINVAL; in l2_write()
95 { .compatible = "sifive,fu540-c000-ccache" },
139 if (this_leaf->level == 2) in l2_get_priv_group()
188 return -ENODEV; in sifive_l2_init()
191 return -ENODEV; in sifive_l2_init()
195 return -ENOMEM; in sifive_l2_init()
/linux-5.10/drivers/gpio/
Dgpio-sifive.c1 // SPDX-License-Identifier: GPL-2.0
48 spin_lock_irqsave(&chip->gc.bgpio_lock, flags); in sifive_gpio_set_ie()
49 trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0; in sifive_gpio_set_ie()
50 regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset), in sifive_gpio_set_ie()
52 regmap_update_bits(chip->regs, SIFIVE_GPIO_FALL_IE, BIT(offset), in sifive_gpio_set_ie()
54 regmap_update_bits(chip->regs, SIFIVE_GPIO_HIGH_IE, BIT(offset), in sifive_gpio_set_ie()
56 regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset), in sifive_gpio_set_ie()
58 spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags); in sifive_gpio_set_ie()
67 if (offset < 0 || offset >= gc->ngpio) in sifive_gpio_irq_set_type()
68 return -EINVAL; in sifive_gpio_irq_set_type()
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/linux-5.10/drivers/pwm/
Dpwm-sifive.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 SiFive
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
8 * - When changing both duty cycle and period, we cannot prevent in
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
65 mutex_lock(&ddata->lock); in pwm_sifive_request()
66 ddata->user_count++; in pwm_sifive_request()
67 mutex_unlock(&ddata->lock); in pwm_sifive_request()
76 mutex_lock(&ddata->lock); in pwm_sifive_free()
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/linux-5.10/drivers/tty/serial/
Dsifive.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2018-2019 SiFive
18 * - drivers/tty/serial/pxa.c
19 * - drivers/tty/serial/amba-pl011.c
20 * - drivers/tty/serial/uartlite.c
21 * - drivers/tty/serial/omap-serial.c
22 * - drivers/pwm/pwm-sifive.c
25 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
26 * SiFive FE310-G000 v2p3
27 * - The tree/master/src/main/scala/devices/uart directory of
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