Lines Matching +full:fu540 +full:- +full:c000
1 // SPDX-License-Identifier: GPL-2.0
48 spin_lock_irqsave(&chip->gc.bgpio_lock, flags); in sifive_gpio_set_ie()
49 trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0; in sifive_gpio_set_ie()
50 regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset), in sifive_gpio_set_ie()
52 regmap_update_bits(chip->regs, SIFIVE_GPIO_FALL_IE, BIT(offset), in sifive_gpio_set_ie()
54 regmap_update_bits(chip->regs, SIFIVE_GPIO_HIGH_IE, BIT(offset), in sifive_gpio_set_ie()
56 regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset), in sifive_gpio_set_ie()
58 spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags); in sifive_gpio_set_ie()
67 if (offset < 0 || offset >= gc->ngpio) in sifive_gpio_irq_set_type()
68 return -EINVAL; in sifive_gpio_irq_set_type()
70 chip->trigger[offset] = trigger; in sifive_gpio_irq_set_type()
86 gc->direction_input(gc, offset); in sifive_gpio_irq_enable()
88 spin_lock_irqsave(&gc->bgpio_lock, flags); in sifive_gpio_irq_enable()
90 regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); in sifive_gpio_irq_enable()
91 regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); in sifive_gpio_irq_enable()
92 regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); in sifive_gpio_irq_enable()
93 regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); in sifive_gpio_irq_enable()
94 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in sifive_gpio_irq_enable()
97 assign_bit(offset, &chip->irq_state, 1); in sifive_gpio_irq_enable()
107 assign_bit(offset, &chip->irq_state, 0); in sifive_gpio_irq_disable()
120 spin_lock_irqsave(&gc->bgpio_lock, flags); in sifive_gpio_irq_eoi()
122 regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); in sifive_gpio_irq_eoi()
123 regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); in sifive_gpio_irq_eoi()
124 regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); in sifive_gpio_irq_eoi()
125 regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); in sifive_gpio_irq_eoi()
126 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in sifive_gpio_irq_eoi()
132 .name = "sifive-gpio",
162 struct device *dev = &pdev->dev; in sifive_gpio_probe()
163 struct device_node *node = pdev->dev.of_node; in sifive_gpio_probe()
172 return -ENOMEM; in sifive_gpio_probe()
174 chip->base = devm_platform_ioremap_resource(pdev, 0); in sifive_gpio_probe()
175 if (IS_ERR(chip->base)) { in sifive_gpio_probe()
177 return PTR_ERR(chip->base); in sifive_gpio_probe()
180 chip->regs = devm_regmap_init_mmio(dev, chip->base, in sifive_gpio_probe()
182 if (IS_ERR(chip->regs)) in sifive_gpio_probe()
183 return PTR_ERR(chip->regs); in sifive_gpio_probe()
189 return -ENXIO; in sifive_gpio_probe()
195 return -ENODEV; in sifive_gpio_probe()
200 return -ENODEV; in sifive_gpio_probe()
203 ret = bgpio_init(&chip->gc, dev, 4, in sifive_gpio_probe()
204 chip->base + SIFIVE_GPIO_INPUT_VAL, in sifive_gpio_probe()
205 chip->base + SIFIVE_GPIO_OUTPUT_VAL, in sifive_gpio_probe()
207 chip->base + SIFIVE_GPIO_OUTPUT_EN, in sifive_gpio_probe()
208 chip->base + SIFIVE_GPIO_INPUT_EN, in sifive_gpio_probe()
216 regmap_write(chip->regs, SIFIVE_GPIO_RISE_IE, 0); in sifive_gpio_probe()
217 regmap_write(chip->regs, SIFIVE_GPIO_FALL_IE, 0); in sifive_gpio_probe()
218 regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IE, 0); in sifive_gpio_probe()
219 regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0); in sifive_gpio_probe()
220 chip->irq_state = 0; in sifive_gpio_probe()
222 chip->gc.base = -1; in sifive_gpio_probe()
223 chip->gc.ngpio = ngpio; in sifive_gpio_probe()
224 chip->gc.label = dev_name(dev); in sifive_gpio_probe()
225 chip->gc.parent = dev; in sifive_gpio_probe()
226 chip->gc.owner = THIS_MODULE; in sifive_gpio_probe()
227 girq = &chip->gc.irq; in sifive_gpio_probe()
228 girq->chip = &sifive_gpio_irqchip; in sifive_gpio_probe()
229 girq->fwnode = of_node_to_fwnode(node); in sifive_gpio_probe()
230 girq->parent_domain = parent; in sifive_gpio_probe()
231 girq->child_to_parent_hwirq = sifive_gpio_child_to_parent_hwirq; in sifive_gpio_probe()
232 girq->handler = handle_bad_irq; in sifive_gpio_probe()
233 girq->default_type = IRQ_TYPE_NONE; in sifive_gpio_probe()
236 return gpiochip_add_data(&chip->gc, chip); in sifive_gpio_probe()
241 { .compatible = "sifive,fu540-c000-gpio" },