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Searched full:emc_cfg (Results 1 – 9 of 9) sorted by relevance

/linux-5.10/drivers/memory/tegra/
Dtegra30-emc.c34 #define EMC_CFG 0x00c macro
340 u32 emc_cfg; member
513 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG); in emc_prepare_timing_change()
536 if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) { in emc_prepare_timing_change()
537 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE; in emc_prepare_timing_change()
538 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
650 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST, in emc_prepare_timing_change()
651 emc->regs + EMC_CFG); in emc_prepare_timing_change()
678 val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST); in emc_prepare_timing_change()
681 emc->emc_cfg |= EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
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Dtegra210-emc-cc-r21021.c480 u32 emc_cfg, emc_cfg_o, emc_cfg_update, del, value; in tegra210_emc_r21021_periodic_compensation() local
501 emc_cfg_o = emc_readl(emc, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
502 emc_cfg = emc_cfg_o & ~(EMC_CFG_DYN_SELF_REF | in tegra210_emc_r21021_periodic_compensation()
510 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
565 emc_writel(emc, emc_cfg_o, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
611 u32 emc_auto_cal_config, auto_cal_en, emc_cfg, emc_sel_dpd_ctrl; in tegra210_emc_r21021_set_clock() local
648 emc_readl(emc, EMC_CFG); in tegra210_emc_r21021_set_clock()
665 emc_cfg = next->burst_regs[EMC_CFG_INDEX]; in tegra210_emc_r21021_set_clock()
666 emc_cfg &= ~(EMC_CFG_DYN_SELF_REF | EMC_CFG_DRAM_ACPD | in tegra210_emc_r21021_set_clock()
720 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_set_clock()
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Dtegra124-emc.c32 #define EMC_CFG 0xc macro
449 u32 emc_cfg; member
590 val = readl(emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
593 writel(val, emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
675 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; in tegra_emc_prepare_timing_change()
676 emc_ccfifo_writel(emc, val, EMC_CFG); in tegra_emc_prepare_timing_change()
812 if (timing->emc_cfg & EMC_CFG_PWR_MASK) in tegra_emc_complete_timing_change()
813 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
859 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
922 EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg") in load_one_timing_from_dt()
Dtegra20-emc.c411 u32 emc_cfg, emc_dbg; in emc_setup_hw() local
413 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
419 if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) && in emc_setup_hw()
420 !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) { in emc_setup_hw()
427 emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; in emc_setup_hw()
428 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
Dtegra210-emc.h26 #define EMC_CFG 0xc macro
Dtegra210-emc-core.c245 EMC_CFG,
/linux-5.10/arch/arm/mach-tegra/
Dsleep-tegra30.S18 #define EMC_CFG 0xc macro
457 ldr r1, [r0, #EMC_CFG]
459 str r1, [r0, #EMC_CFG]
525 ldr r1, [r5, #0x0] @ restore EMC_CFG
526 str r1, [r0, #EMC_CFG]
547 .word TEGRA_EMC_BASE + EMC_CFG @0x0
558 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
566 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
574 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
775 ldr r1, [r0, #EMC_CFG]
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Dsleep-tegra20.S23 #define EMC_CFG 0xc macro
213 ldr r1, [r0, #EMC_CFG]
215 str r1, [r0, #EMC_CFG]
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-emc.yaml90 value of the EMC_CFG register for this set of timings