Lines Matching full:emc_cfg
34 #define EMC_CFG 0x00c macro
340 u32 emc_cfg; member
513 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG); in emc_prepare_timing_change()
536 if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) { in emc_prepare_timing_change()
537 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE; in emc_prepare_timing_change()
538 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
650 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST, in emc_prepare_timing_change()
651 emc->regs + EMC_CFG); in emc_prepare_timing_change()
678 val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST); in emc_prepare_timing_change()
681 emc->emc_cfg |= EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
683 emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
685 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
779 emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE; in emc_complete_timing_change()
780 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_complete_timing_change()
1010 u32 fbio_cfg5, emc_cfg, emc_dbg; in emc_setup_hw() local
1016 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
1019 emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; in emc_setup_hw()
1024 emc_cfg |= EMC_CLKCHANGE_PD_ENABLE; in emc_setup_hw()
1025 emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE; in emc_setup_hw()
1029 emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE; in emc_setup_hw()
1030 emc_cfg &= ~EMC_CLKCHANGE_PD_ENABLE; in emc_setup_hw()
1034 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()