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/qemu/hw/misc/
H A Dsbsa_ec.c23 #define TYPE_SBSA_SECURE_EC "sbsa-ec"
34 qemu_log_mask(LOG_GUEST_ERROR, "sbsa-ec: no readable registers"); in sbsa_ec_read()
51 "sbsa-ec: unknown power command"); in sbsa_ec_write()
54 qemu_log_mask(LOG_GUEST_ERROR, "sbsa-ec: unknown EC register"); in sbsa_ec_write()
71 memory_region_init_io(&s->iomem, obj, &sbsa_ec_ops, s, "sbsa-ec", in sbsa_ec_init()
/qemu/bsd-user/aarch64/
H A Dtarget_arch_cpu.h49 int trapnr, ec, fsc, si_code, si_signo; in target_cpu_loop() local
113 /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */ in target_cpu_loop()
114 ec = syn_get_ec(env->exception.syndrome); in target_cpu_loop()
115 assert(ec == EC_DATAABORT || ec == EC_INSNABORT); in target_cpu_loop()
117 /* Both EC have the same format for FSC, or close enough. */ in target_cpu_loop()
/qemu/hw/char/
H A Dsclpconsole.c261 SCLPEventClass *ec = SCLP_EVENT_CLASS(klass); in console_class_init() local
266 ec->init = console_init; in console_class_init()
267 ec->get_send_mask = send_mask; in console_class_init()
268 ec->get_receive_mask = receive_mask; in console_class_init()
269 ec->can_handle_event = can_handle_event; in console_class_init()
270 ec->read_event_data = read_event_data; in console_class_init()
271 ec->write_event_data = write_event_data; in console_class_init()
H A Dsclpconsole-lm.c345 SCLPEventClass *ec = SCLP_EVENT_CLASS(klass); in console_class_init() local
350 ec->init = console_init; in console_class_init()
351 ec->get_send_mask = send_mask; in console_class_init()
352 ec->get_receive_mask = receive_mask; in console_class_init()
353 ec->can_handle_event = can_handle_event; in console_class_init()
354 ec->read_event_data = read_event_data; in console_class_init()
355 ec->write_event_data = write_event_data; in console_class_init()
/qemu/hw/s390x/
H A Devent-facility.c129 SCLPEventClass *ec; in handle_write_event_buf() local
136 ec = SCLP_EVENT_GET_CLASS(event); in handle_write_event_buf()
138 if (ec->write_event_data && in handle_write_event_buf()
139 ec->can_handle_event(event_buf->type)) { in handle_write_event_buf()
140 rc = ec->write_event_data(event, event_buf); in handle_write_event_buf()
202 SCLPEventClass *ec; in handle_sccb_read_events() local
215 ec = SCLP_EVENT_GET_CLASS(event); in handle_sccb_read_events()
217 if (mask & ec->get_send_mask()) { in handle_sccb_read_events()
218 if (ec->read_event_data(event, event_buf, &slen)) { in handle_sccb_read_events()
/qemu/docs/system/devices/
H A Dusb-u2f.rst51 * ec x509 certificate
52 * ec private key
76 * ``certificate.pem``: ec x509 certificate
77 * ``private-key.pem``: ec private key
/qemu/hw/sensor/
H A Demc141x.c282 EMC141XClass *ec = EMC141X_CLASS(klass); in emc1413_class_init() local
285 ec->model = EMC1413_DEVICE_ID; in emc1413_class_init()
286 ec->sensors_count = 3; in emc1413_class_init()
291 EMC141XClass *ec = EMC141X_CLASS(klass); in emc1414_class_init() local
294 ec->model = EMC1414_DEVICE_ID; in emc1414_class_init()
295 ec->sensors_count = 4; in emc1414_class_init()
/qemu/scripts/
H A Du2f-setup-gen.py18 from cryptography.hazmat.primitives.asymmetric import ec
58 Generate an ec key pair.
64 privkey = ec.generate_private_key(ec.SECP256R1, default_backend())
H A Ddevice-crash-test377 ec = vm.exitcode()
380 if exc is not None or ec != 0:
383 'exitcode':ec,
/qemu/linux-user/aarch64/
H A Dcpu_loop.c34 int trapnr, ec, fsc, si_code, si_signo; in cpu_loop() local
70 ec = syn_get_ec(env->exception.syndrome); in cpu_loop()
71 switch (ec) { in cpu_loop()
74 /* Both EC have the same format for FSC, or close enough. */ in cpu_loop()
/qemu/scripts/coccinelle/
H A Duse-error_fatal.cocci5 expression ERR, EC, FAIL;
19 - exit(EC);
/qemu/linux-user/include/host/aarch64/
H A Dhost-signal.h59 struct esr_context const *ec = (struct esr_context const *)hdr; in host_signal_write() local
60 uint64_t esr = ec->esr; in host_signal_write()
62 /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ in host_signal_write()
/qemu/target/arm/hvf/
H A Dtrace-events10 hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]"
H A Dhvf.c1918 uint32_t ec = syn_get_ec(syndrome); in hvf_vcpu_exec() local
1939 switch (ec) { in hvf_vcpu_exec()
2087 trace_hvf_exit(syndrome, ec, env->pc); in hvf_vcpu_exec()
2088 error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec); in hvf_vcpu_exec()
/qemu/target/arm/
H A Dsyndrome.h30 /* Valid Syndrome Register EC field values */
100 static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec) in syn_set_ec() argument
102 return deposit32(syn, ARM_EL_EC_SHIFT, ARM_EL_EC_LENGTH, ec); in syn_set_ec()
/qemu/target/s390x/
H A Dcpu_models.c70 CPUDEF_INIT(0x2094, 9, 1, 40, 0x00000000U, "z9EC", "IBM System z9 EC GA1"),
71 CPUDEF_INIT(0x2094, 9, 2, 40, 0x00000000U, "z9EC.2", "IBM System z9 EC GA2"),
73 CPUDEF_INIT(0x2094, 9, 3, 40, 0x00000000U, "z9EC.3", "IBM System z9 EC GA3"),
76 CPUDEF_INIT(0x2097, 10, 1, 43, 0x00000000U, "z10EC", "IBM System z10 EC GA1"),
77 CPUDEF_INIT(0x2097, 10, 2, 43, 0x00000000U, "z10EC.2", "IBM System z10 EC GA2"),
79 CPUDEF_INIT(0x2097, 10, 3, 43, 0x00000000U, "z10EC.3", "IBM System z10 EC GA3"),
338 /* prefer the model with the same cpu type, esp. don't take the BC for EC */ in s390_find_cpu_def()
H A Dcpu_models.h26 uint8_t ec_ga; /* EC GA version (on which also the BC is based) */
H A Dcpu_models_system.c291 /* ec and corresponding bc are identical */ in qmp_query_cpu_model_comparison()
/qemu/roms/
H A DMakefile17 pxe-rom-rtl8139 efi-rom-rtl8139 : VID := 10ec
121 -ec ipxe/src/bin-x86_64-efi/$(VID)$(DID).efidrv \
/qemu/docs/specs/
H A Dspdm.rst62 $ openssl req -nodes -newkey ec:param.pem -keyout end_responder.key \
/qemu/pc-bios/
H A DREADME30 10ec:8139 -> pxe-rtl8139.rom
/qemu/tests/qtest/
H A Dfw_cfg-test.c70 s = qtest_init("-uuid 4600cb32-38ec-4b2f-8acb-81c6ea54f2d8"); in test_fw_cfg_uuid()
/qemu/docs/devel/
H A Dqapi-domain.rst701 :alt int ec: An error code, like the type you're used to.
713 :alt int ec: An error code, like the type you're used to.
/qemu/target/arm/tcg/
H A Dtlb_helper.c184 * (and indeed syndrome does not have the EC field in it, in arm_deliver_fault()
/qemu/docs/devel/migration/
H A Dqpl-compression.rst78 ec:02.0 System peripheral: Intel Corporation Device 0cfe

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