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Searched full:dt (Results 1 – 25 of 65) sorted by relevance

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/qemu/target/i386/tcg/system/
H A Dsmm_helper.c40 SegmentCache *dt; in do_smm_enter() local
58 dt = &env->segs[i]; in do_smm_enter()
60 x86_stw_phys(cs, sm_state + offset, dt->selector); in do_smm_enter()
61 x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff); in do_smm_enter()
62 x86_stl_phys(cs, sm_state + offset + 4, dt->limit); in do_smm_enter()
63 x86_stq_phys(cs, sm_state + offset + 8, dt->base); in do_smm_enter()
143 dt = &env->segs[i]; in do_smm_enter()
149 x86_stl_phys(cs, sm_state + 0x7fa8 + i * 4, dt->selector); in do_smm_enter()
150 x86_stl_phys(cs, sm_state + offset + 8, dt->base); in do_smm_enter()
151 x86_stl_phys(cs, sm_state + offset + 4, dt->limit); in do_smm_enter()
[all …]
/qemu/target/i386/tcg/user/
H A Dseg_helper.c48 SegmentCache *dt; in do_interrupt_user() local
53 dt = &env->idt; in do_interrupt_user()
59 ptr = dt->base + (intno << shift); in do_interrupt_user()
/qemu/target/i386/tcg/
H A Dseg_helper.c153 SegmentCache *dt; in load_segment_ra() local
158 dt = &env->ldt; in load_segment_ra()
160 dt = &env->gdt; in load_segment_ra()
163 if ((index + 7) > dt->limit) { in load_segment_ra()
166 ptr = dt->base + index; in load_segment_ra()
339 SegmentCache *dt; in switch_tss_ra() local
558 dt = &env->gdt; in switch_tss_ra()
560 if ((index + 7) > dt->limit) { in switch_tss_ra()
563 ptr = dt->base + index; in switch_tss_ra()
689 SegmentCache *dt; in do_interrupt_protected() local
[all …]
/qemu/docs/sphinx-static/
H A Dtheme_overrides.css19 .rst-content dl:not(.docutils) dt {
281 dl.field-list > dt:first-of-type, dl.field-list > dd:first-of-type {
285 dl.field-list > dt:last-of-type, dl.field-list > dd:last-of-type {
290 dl.field-list > dt {
/qemu/include/system/
H A Ddevice_tree.h31 * @fdt: pointer to the dt blob
52 * @fdt: pointer to the dt blob
77 * @fdt: pointer to the dt blob
/qemu/hw/core/
H A Dsysbus-fdt.c82 * @node_path: host dt node path where the property is supposed to be
334 error_report("%s Does the host dt node combine XGBE/PHY?", __func__); in add_amd_xgbe_fdt_node()
350 * clock handles fetched from host dt are in be32 layout whereas in add_amd_xgbe_fdt_node()
420 /* DT compatible matching */
445 * add_tpm_tis_fdt_node: Create a DT node for TPM TIS
/qemu/target/mips/tcg/
H A Ddsp_helper.c1099 DSP32Value dt; \
1102 dt.sw[0] = rt; \
1104 for (i = 0; i < ARRAY_SIZE(dt.element); i++) { \
1105 dt.element[i] = mipsdsp_##func(dt.element[i], env); \
1108 return (target_long)dt.sw[0]; \
1119 DSP64Value dt; \
1122 dt.sl[0] = rt; \
1124 for (i = 0; i < ARRAY_SIZE(dt.element); i++) { \
1125 dt.element[i] = mipsdsp_##func(dt.element[i], env); \
1128 return dt.sl[0]; \
[all …]
/qemu/target/i386/
H A Dhelper.c569 SegmentCache *dt; in cpu_x86_get_descr_debug() local
575 dt = &env->ldt; in cpu_x86_get_descr_debug()
577 dt = &env->gdt; in cpu_x86_get_descr_debug()
579 ptr = dt->base + index; in cpu_x86_get_descr_debug()
580 if ((index + 7) > dt->limit in cpu_x86_get_descr_debug()
/qemu/system/
H A Ddevice_tree.c74 error_report("%s Couldn't create dt: %s", __func__, fdt_strerror(ret)); in create_device_tree()
213 /* load_device_tree_from_sysfs: extract the dt blob from host sysfs */
279 error_setg(errp, "%s: abort parsing dt for %s node units: %s", in qemu_fdt_node_unit_path()
333 error_setg(errp, "%s: abort parsing dt for %s/%s: %s", in qemu_fdt_node_path()
H A Drtc.c115 if (sscanf(startdate, "%d-%d-%dT%d:%d:%d", &tm.tm_year, &tm.tm_mon, in configure_rtc_base_datetime()
/qemu/hw/sparc64/
H A Dtrace-events22 …real_limit, const char *dis, void *p, uint64_t limit, uint64_t t, uint64_t dt) "%s set_limit limit…
/qemu/hw/intc/
H A Darm_gicv3_its.c292 uint64_t entry_addr = table_entry_addr(s, &s->dt, devid, &res); in get_dte()
366 if (devid >= s->dt.num_entries) { in lookup_ite()
369 who, devid, s->dt.num_entries); in lookup_ite()
601 if (devid >= s->dt.num_entries) { in process_mapti()
604 __func__, devid, s->dt.num_entries); in process_mapti()
673 if (devid >= s->dt.num_entries) { in process_vmapti()
676 __func__, devid, s->dt.num_entries); in process_vmapti()
809 entry_addr = table_entry_addr(s, &s->dt, devid, &res); in update_dte()
834 if (devid >= s->dt.num_entries) { in process_mapd()
837 devid, s->dt.num_entries); in process_mapd()
[all …]
/qemu/hw/i386/
H A Dmeson.build17 …n: 'CONFIG_MICROVM', if_true: files('x86-common.c', 'microvm.c', 'acpi-microvm.c', 'microvm-dt.c'))
/qemu/include/hw/vfio/
H A Dvfio-platform.h59 char *compat; /* DT compatible values, separated by NUL */
/qemu/tests/tcg/s390x/
H A Dsam.S41 /* DT = 0b11 (region-first-table), TL = 3 (2k entries) */
/qemu/include/hw/ppc/
H A Dspapr_xive.h34 /* DT */
H A Dspapr_irq.h77 void (*dt)(SpaprInterruptController *intc, uint32_t nr_servers, member
/qemu/include/hw/intc/
H A Darm_gicv3_its_common.h79 TableDesc dt; member
/qemu/util/
H A Derror-report.c175 g_autoptr(GDateTime) dt = g_date_time_new_now_utc(); in real_time_iso8601()
176 return g_date_time_format_iso8601(dt); in real_time_iso8601()
/qemu/hw/arm/
H A Dsabrelite.c25 /* No board ID, we boot from DT tree */
/qemu/docs/system/arm/
H A Dsabrelite.rst84 Device Tree Control > Provider of DTB for DT Control > Embedded DTB
H A Dbananapi_m2u.rst112 Device Tree Control > Provider for DTB for DT Control > Embedded DTB
/qemu/include/hw/i386/
H A Dx86-iommu.h65 bool dt_supported; /* Whether vIOMMU supports DT */
/qemu/include/hw/xen/interface/
H A Darch-arm.h309 * Based on the property clock-frequency in the DT timer node.
314 * the value in the guest DT.
/qemu/tcg/
H A Dtcg-op-vec.c774 TCGTemp *dt = tcgv_vec_temp(d); in tcg_gen_cmpsel_vec() local
779 TCGArg di = temp_arg(dt); in tcg_gen_cmpsel_vec()
787 tcg_debug_assert(dt->base_type >= type); in tcg_gen_cmpsel_vec()

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