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/linux-6.8/drivers/memory/samsung/
Dexynos5422-dmc.c104 * Covers frequency and voltage settings of the DMC operating mode.
112 * struct exynos5_dmc - main structure describing DMC device
113 * @dev: DMC device
238 static int exynos5_counters_set_event(struct exynos5_dmc *dmc) in exynos5_counters_set_event() argument
242 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_set_event()
243 if (!dmc->counter[i]) in exynos5_counters_set_event()
245 ret = devfreq_event_set_event(dmc->counter[i]); in exynos5_counters_set_event()
252 static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc) in exynos5_counters_enable_edev() argument
256 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_enable_edev()
257 if (!dmc->counter[i]) in exynos5_counters_enable_edev()
[all …]
DKconfig17 This adds driver for Samsung Exynos5422 SoC DMC (Dynamic Memory
19 Frequency Scaling in DMC and DRAM. It also supports changing timings
DMakefile2 obj-$(CONFIG_EXYNOS5422_DMC) += exynos5422-dmc.o
/linux-6.8/drivers/gpu/drm/i915/display/
Dintel_dmc.c34 * DOC: DMC Firmware Support
36 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
71 return i915->display.dmc.dmc; in i915_to_dmc()
82 * New DMC additions should not use this. This is used solely to remain
83 * compatible with systems that have not yet updated DMC blobs to use
149 /* 0x09 for DMC */
152 /* Includes the DMC specific header in dwords */
167 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
209 /* DMC container header length in dwords */
225 /* DMC binary header length */
[all …]
Dintel_display_power_map.c358 /* Handled by the DMC firmware */
372 /* Handled by the DMC firmware */
611 * ICL PW_0/PG_0 domains (HW/DMC control):
616 * ICL PW_1/PG_1 domains (HW/DMC control):
717 /* Handled by the DMC firmware */
1034 * RKL PW_1/PG_1 domains (under HW/DMC control):
1041 * RKL PW_0/PG_0 domains (under HW/DMC control):
1283 * XELPD PW_1/PG_1 domains (under HW/DMC control):
1288 * XELPD PW_0/PW_1 domains (under HW/DMC control):
Dintel_dmc_regs.h63 #define DMC_EVT_CTL_EVENT_ID_VBLANK_A 0x32 /* main DMC */
Dintel_display_core.h354 struct intel_dmc *dmc; member
356 } dmc; member
/linux-6.8/Documentation/devicetree/bindings/edac/
Ddmc-520.yaml4 $id: http://devicetree.org/schemas/edac/dmc-520.yaml#
7 title: ARM DMC-520 EDAC
13 DMC-520 node is defined to describe DRAM error detection and correction.
20 - const: brcm,dmc-520
21 - const: arm,dmc-520
56 dmc0: dmc@200000 {
57 compatible = "brcm,dmc-520", "arm,dmc-520";
/linux-6.8/Documentation/admin-guide/perf/
Dthunderx2-pmu.rst6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
13 The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8
16 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
22 L3C devices. Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
/linux-6.8/Documentation/devicetree/bindings/memory-controllers/
Dsamsung,exynos5422-dmc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
16 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
22 switch the DMC and memory frequency.
27 - const: samsung,exynos5422-dmc
62 - description: DMC internal performance event counters in DREX0
63 - description: DMC internal performance event counters in DREX1
112 compatible = "samsung,exynos5422-dmc";
Drockchip,rk3399-dmc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
7 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
15 - rockchip,rk3399-dmc
34 DMC regulator supply.
363 compatible = "rockchip,rk3399-dmc";
/linux-6.8/Documentation/devicetree/bindings/interconnect/
Dsamsung,exynos-bus.yaml49 VDD_MIF |--- DMC (Dynamic Memory Controller)
93 VDD_INT |--- DMC (parent device, Dynamic Memory Controller)
110 VDD_MIF |--- DMC (Dynamic Memory Controller)
225 bus-dmc {
287 dmc: bus-dmc {
303 interconnects = <&dmc>;
314 interconnects = <&leftbus &dmc>;
/linux-6.8/include/soc/amlogic/
Dmeson_ddr_pmu.h35 u64 channel_cnt[MAX_CHANNEL_NUM]; /* To save a DMC bandwidth-monitor channel counter */
48 int dmc_nr; /* The number of dmc controller */
49 int chann_nr; /* The number of dmc bandwidth monitor channels */
/linux-6.8/drivers/net/ethernet/sun/
Dniu.h19 #define DMC 0x600000UL macro
1978 #define RXDMA_CFIG1(IDX) (DMC + 0x00000UL + (IDX) * 0x200UL)
1984 #define RXDMA_CFIG2(IDX) (DMC + 0x00008UL + (IDX) * 0x200UL)
1990 #define RBR_CFIG_A(IDX) (DMC + 0x00010UL + (IDX) * 0x200UL)
1996 #define RBR_CFIG_B(IDX) (DMC + 0x00018UL + (IDX) * 0x200UL)
2026 #define RBR_KICK(IDX) (DMC + 0x00020UL + (IDX) * 0x200UL)
2029 #define RBR_STAT(IDX) (DMC + 0x00028UL + (IDX) * 0x200UL)
2032 #define RBR_HDH(IDX) (DMC + 0x00030UL + (IDX) * 0x200UL)
2035 #define RBR_HDL(IDX) (DMC + 0x00038UL + (IDX) * 0x200UL)
2038 #define RCRCFIG_A(IDX) (DMC + 0x00040UL + (IDX) * 0x200UL)
[all …]
/linux-6.8/drivers/cpufreq/
Ds5pv210-cpufreq.c194 * ch: DMC port number 0 or 1
207 pr_err("Cannot find DMC port\n"); in s5pv210_set_refresh()
536 /* Find current refresh counter and frequency each DMC */ in s5pv210_cpu_init()
599 * and DMC controller registers directly and remove static mappings in s5pv210_cpufreq_probe()
632 for_each_compatible_node(np, NULL, "samsung,s5pv210-dmc") { in s5pv210_cpufreq_probe()
633 id = of_alias_get_id(np, "dmc"); in s5pv210_cpufreq_probe()
635 dev_err(dev, "failed to get alias of dmc node '%pOFn'\n", np); in s5pv210_cpufreq_probe()
643 dev_err(dev, "failed to map dmc%d registers\n", id); in s5pv210_cpufreq_probe()
652 dev_err(dev, "failed to find dmc%d node\n", id); in s5pv210_cpufreq_probe()
/linux-6.8/Documentation/devicetree/bindings/perf/
Damlogic,g12-ddr-pmu.yaml27 - description: DMC bandwidth register space.
28 - description: DMC PLL register space.
/linux-6.8/drivers/pmdomain/amlogic/
Dmeson-secure-pwrc.c117 /* DMC is for DDR PHY ana/dig and DMC, and should be always on */
118 SEC_PD(DMC, GENPD_FLAG_ALWAYS_ON),
207 /* DMC0 is for DDR PHY ana/dig and DMC, and should be always on */
209 /* DMC1 is for DDR PHY ana/dig and DMC, and should be always on */
/linux-6.8/drivers/perf/
DKconfig166 in the DDR4 Memory Controller (DMC).
184 tristate "Enable PMU support for the ARM DMC-620 memory controller"
187 Support for PMU events monitoring on the ARM DMC-620 memory
Darm_dmc620_pmu.c3 * ARM DMC-620 memory controller PMU driver
40 * The PMU registers start at 0xA00 in the DMC-620 memory map, and these
522 * DMC 620 PMUs are shared across all cpus and cannot in dmc620_pmu_event_init()
781 MODULE_DESCRIPTION("Perf driver for the ARM DMC-620 memory controller");
Dthunderx2_pmu.c13 /* Each ThunderX2(TX2) Socket has a L3C and DMC UNCORE PMU device.
60 /* DMC event IDs */
87 * Each socket has 3 uncore devices associated with a PMU. The DMC and
493 /* DMC event data_transfers granularity is 16 Bytes, convert it to 64 */ in tx2_uncore_event_update()
498 /* L3C and DMC has 16 and 8 interleave channels respectively. in tx2_uncore_event_update()
/linux-6.8/drivers/edac/
Ddmc520_edac.c4 * EDAC driver for DMC-520 memory controller.
25 /* DMC-520 registers */
43 /* DMC-520 types, masks and bitfields */
632 { .compatible = "arm,dmc-520", },
653 MODULE_DESCRIPTION("DMC-520 ECC driver");
/linux-6.8/drivers/devfreq/
DKconfig133 tristate "ARM RK3399 DMC DEVFREQ Driver"
140 This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
/linux-6.8/Documentation/gpu/
Di915.rst198 DMC Firmware Support
202 :doc: DMC Firmware Support
490 display microcontroller (DMC). The driver is responsible for loading the
492 to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.
564 DMC section in Microcontrollers
566 See `DMC Firmware Support`_
/linux-6.8/arch/arm/boot/dts/samsung/
Ds5pv210.dtsi498 dmc0: dmc@f0000000 {
499 compatible = "samsung,s5pv210-dmc";
503 dmc1: dmc@f1400000 {
504 compatible = "samsung,s5pv210-dmc";
/linux-6.8/Documentation/devicetree/bindings/clock/
Dsamsung,exynos-clock.yaml24 - samsung,exynos3250-cmu-dmc

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