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/linux/Documentation/devicetree/bindings/soc/renesas/
H A Drenesas.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas SH-Mobile, R-Mobile, and R-Ca
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynos9810.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cell
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dwkup_m3_rproc.txt1 TI Wakeup M3 Remoteproc Driver
4 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
5 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
10 Wkup M3 Device Node:
12 A wkup_m3 device node is used to represent the Wakeup M3 processor instance
17 ---
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H A Dqcom,rpm-proc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,rpm-proc.yaml#
5 $schema: http://devicetree.org/meta-schema
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/linux/arch/arm/mm/
H A Dproc-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7m.S
8 * This is the "shell" of the ARMv7-M processor support.
15 #include "proc-macros.S"
32 * - loc - location to jump to for soft reset
105 * This should be able to cover all ARMv7-
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/linux/drivers/soc/ti/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
18 Packets are queued/de-queued by writing/reading descriptor address
40 c-states on AM335x. Also required for rtc and ddr in self-refresh low
44 tristate "TI AMx3 Wkup-M3 IPC Driver"
48 TI AM33XX and AM43XX have a Cortex M
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/linux/Documentation/devicetree/bindings/soc/ti/
H A Dwkup-m3-ipc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/ti/wkup-m
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/linux/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bi
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/linux/arch/arm/mach-versatile/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
52 bool "Include support for Integrator/IM-PD1"
60 The IM-PD1 is an add-on logic module for the Integrator which
62 The IM-PD1 can be found on the Integrator/PP2 platform.
77 bool "Integrator/CM922T-XA10 core module"
83 bool "Integrator/CM926EJ-S core module"
107 bool "Integrator/CM1026EJ-
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/linux/Documentation/devicetree/bindings/mailbox/
H A Dxgene-slimpro-mailbox.txt1 The APM X-Gene SLIMpro mailbox is used to communicate messages between
2 the ARM64 processors and the Cortex M3 (dubbed SLIMpro). It uses a simple
10 - compatible: Should be as "apm,xgene-slimpro-mbox".
12 - reg: Contains the mailbox register address range.
14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
18 - #mbox-cell
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/linux/Documentation/staging/
H A Drpmsg.rst17 flavor of real-time OS.
19 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.
20 Typically, the dual cortex-A9 is running Linux in a SMP configuration,
21 and each of the other three cores (two M3 cores and a DSP) is running
25 hardware accelerators, and therefore are often used to offload CPU-intensiv
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H A Dremoteproc.rst10 of operating system, whether it's Linux or any other flavor of real-time OS.
12 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.
13 In a typical configuration, the dual cortex-A9 is running Linux in a SMP
14 configuration, and each of the other three cores (two M3 cores and a DSP)
22 platform-specifi
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/linux/Documentation/locking/
H A Dhwspinlock.rst12 For example, OMAP4 has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP,
14 is usually running Linux and the slave processors, the M3 and the DSP,
17 A generic hwspinlock framework allows platform-independent drivers to use
22 This is necessary, for example, for Inter-processor communications:
23 on OMAP4, cpu-intensive multimedia tasks are offloaded by the host to the
24 remote M3 an
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/linux/drivers/irqchip/
H A Dirq-nvic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/irq/irq-nvic.c
9 * ARMv7-M CPUs (Cortex-M3/M4)
36 #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS -
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/linux/arch/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
161 The ARM series is a line of low-power-consumption RISC chip designs
163 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
164 manufactured, but legacy ARM-based PC hardware remains popular in
175 supported in LLD until version 14. The combined range is -/+ 256 MiB,
268 Patch phys-to-vir
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/linux/drivers/firmware/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
19 provides a mechanism for inter-processor communication between SCP
61 bool "Add firmware-provided memory map to sysfs" if EXPERT
64 Add the firmware-provided (unmodified) memory map to /sys/firmware/memmap.
68 See also Documentation/ABI/testing/sysfs-firmware-memma
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H A Darm_scpi.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * provides a mechanism for inter-processor communication between SCP's
8 * Cortex M3 and AP.
210 -1, /* GET_CLOCK_INFO */
219 -1, /* SET_DEVICE_PWR_STATE */
220 -
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/linux/drivers/gpio/
H A Dgpio-lpc18xx.c1 // SPDX-License-Identifier: GPL-2.0
58 u32 val = readl_relaxed(ic->base + LPC18XX_GPIO_PIN_IC_ISEL); in lpc18xx_gpio_pin_ic_isel()
65 writel_relaxed(val, ic->base + LPC18XX_GPIO_PIN_IC_ISEL); in lpc18xx_gpio_pin_ic_isel()
71 writel_relaxed(BIT(pin), ic->base + reg); in lpc18xx_gpio_pin_ic_set()
76 struct lpc18xx_gpio_pin_ic *ic = d->chip_data; in lpc18xx_gpio_pin_ic_mask()
80 raw_spin_lock(&ic->lock); in lpc18xx_gpio_pin_ic_mask()
83 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_mask()
87 lpc18xx_gpio_pin_ic_set(ic, d->hwir in lpc18xx_gpio_pin_ic_mask()
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/linux/drivers/mailbox/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
37 will be discovered and possibly managed at probe-time.
54 processer can write data in a channel, and set co-responding register
101 running on the Cortex-M3 rWT
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/linux/drivers/ssb/
H A Dscan.c5 * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
6 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
78 return "SATA XOR-DMA"; in ssb_core_name()
82 return "PCI-E"; in ssb_core_name()
94 return "ARM Cortex M3"; in ssb_core_name()
103 switch (pci_dev->device) { in pcidev_to_chipid()
128 dev_err(&pci_dev->dev, "PCI-ID not in fallback list\n"); in pcidev_to_chipid()
165 switch (bus->bustyp in scan_read32()
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/linux/arch/arm/boot/dts/renesas/
H A Dsh73a0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
8 #include <dt-bindings/clock/sh73a0-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-binding
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H A Dr8a7740.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-binding
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/linux/drivers/net/pcs/
H A Dpcs-rzn1-miic.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/pcs-rzn1-miic.h>
17 #include <dt-bindings/net/pcs-rzn1-miic.h>
52 #define MIIC_MODCTRL_CONF_NONE -1
55 * struct modctrl_match - Matchin
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/linux/drivers/clk/mvebu/
H A Darmada-37xx-periph.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 * TBG-A-P --| | | | | | ______
12 * TBG-B-
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/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77960.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a7796-cpg-mss
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