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/qemu/docs/system/arm/
H A Daspeed.rst45 * Interrupt Controller (VIC)
46 * Timer Controller
47 * RTC Controller
48 * I2C Controller, including the new register interface of the AST2600
51 * X-DMA Controller (basic interface)
52 * Static Memory Controller (SMC or FMC) - Only SPI Flash support
53 * SPI Memory Controller
54 * USB 2.0 Controller
56 * SDRAM controller (dummy interface for basic settings and training)
57 * Watchdog Controller
[all …]
H A Draspi.rst22 * Interrupt controller
23 * DMA controller
24 * Clock and reset controller (CPRMAN)
26 * GPIO controller
31 * GPIO controller
32 * SD/MMC host controller
34 * USB2 host controller (DWC2 and MPHI)
35 * MailBox controller (MBOX)
37 * Peripheral SPI controller (SPI)
38 * Broadcom Serial Controller (I2C)
[all …]
H A Dstm32.rst36 * SPI controller
38 * Timer controller (TIMER)
39 * Reset and Clock Controller (RCC) (STM32F4 only, reset and enable only)
45 * Controller Area Network (CAN)
48 * DMA controller
49 * Ethernet controller
51 * GPIO controller
52 * I2C controller
53 * Inter-Integrated Sound (I2S) controller
56 * Real-Time Clock (RTC) controller
[all …]
H A Dvexpress.rst18 - PL181 SD controller
22 - I2C controller
24 - PL111 LCD display controller
32 - USB controller (Philips ISP1761)
38 - HDLCD controller (``vexpress-a15``)
40 - PL341 dynamic memory controller
41 - DMA330 DMA controller
42 - PL354 static memory controller
43 - BP147 TrustZone Protection Controller
44 - TrustZone Address Space Controller
H A Dnuvoton.rst44 * Clock and reset controller (CLK)
45 * Timer controller (TIM)
47 * DDR4 memory controller (dummy interface indicating memory training is done)
52 * GPIO controller
55 * SMBus controller (SMBF)
56 * Ethernet controller (EMC)
58 * Peripheral SPI controller (PSPI)
65 * Keyboard and mouse controller interface (KBCI)
66 * Keyboard Controller Style (KCS) channels
74 * Ethernet controller (GMAC)
H A Dcubieboard.rst15 - USB controller
16 - SATA controller
17 - TWI (I2C) controller
18 - SPI controller
H A Dnrf.rst23 * Clock controller
26 * GPIO controller
34 * Real-Time Clock (RTC) controller
36 * SPI controller
H A Db-l475e-iot01a.rst18 - STM32L4x5 EXTI (Extended interrupts and events controller)
19 - STM32L4x5 SYSCFG (System configuration controller)
31 - SPI controller
32 - Timer controller (TIMER)
/qemu/hw/display/
H A Dvga_regs.h32 #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
33 #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
34 #define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */
35 #define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */
36 #define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */
51 #define VGA_CRT_IC 0x3D4 /* CRT Controller Index - color emulation */
52 #define VGA_CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */
53 #define VGA_ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */
54 #define VGA_GFX_I 0x3CE /* Graphics Controller Index */
60 #define VGA_CRT_C 0x19 /* Number of CRT Controller Registers */
[all …]
/qemu/docs/system/devices/
H A Dnvme.rst11 * Configuration of `Optional Features`_ such as `Controller Memory Buffer`_,
18 Controller Emulation
21 The QEMU emulated NVMe controller implements version 1.4 of the NVM Express
29 The simplest way to attach an NVMe controller on the QEMU PCI bus is to add the
61 controller. We emulate version 5 of this log page.
107 parameter on the controller device).
112 Additional features becomes available if the controller device (``nvme``) is
130 and may only be attached to a single controller at a time. Shared namespaces
150 attachable to a single controller at a time. Additionally it will not be
151 attached to any controller initially (due to ``detached=on``) or to hotplugged
[all …]
H A Dusb.rst4 QEMU can emulate a PCI UHCI, OHCI, EHCI or XHCI USB controller. You can
12 XHCI controller support
24 only controller you need. With only a single USB controller (and
29 EHCI controller support
34 devices. The companion controller setup is more convenient to use
39 controllers for USB 1.1 devices too. Each controller creates its own
41 1.1 bus driven by the UHCI controller and one USB 2.0 bus driven by
42 the EHCI controller. Devices must be attached to the correct
43 controller manually.
45 The easiest way to add a UHCI controller to a ``pc`` machine is the
[all …]
/qemu/hw/arm/
H A DKconfig62 select PL310 # cache controller
81 select PL310 # cache controller
94 select PL110 # pl111 LCD controller
176 select PL080 # DMA controller
179 select PL310 # cache controller
264 select PL080 # DMA controller
294 select PL310 # cache controller
466 select PL310 # cache controller
480 select PL310 # cache controller
520 select PL310 # cache controller
[all …]
H A Dbcm2838.c81 /* bcm2836 interrupt controller (and mailboxes, etc.) */ in bcm2838_realize()
165 /* Connect timers from the CPU to the interrupt controller */ in bcm2838_realize()
179 /* Connect UART0 to the interrupt controller */ in bcm2838_realize()
183 /* Connect AUX / UART1 to the interrupt controller */ in bcm2838_realize()
187 /* Connect VC mailbox to the interrupt controller */ in bcm2838_realize()
191 /* Connect SD host to the interrupt controller */ in bcm2838_realize()
198 /* Connect EMMC and EMMC2 to the interrupt controller */ in bcm2838_realize()
202 /* Connect USB OTG and MPHI to the interrupt controller */ in bcm2838_realize()
208 /* Connect DMA 0-6 to the interrupt controller */ in bcm2838_realize()
218 /* Connect DMA 7-8 to the interrupt controller */ in bcm2838_realize()
[all …]
H A Dbcm2838_peripherals.c21 /* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */
35 /* Extended Mass Media Controller 2 */ in bcm2838_peripherals_init()
82 /* Extended Mass Media Controller 2 */ in bcm2838_peripherals_realize()
109 /* Connect EMMC and EMMC2 to the interrupt controller */ in bcm2838_peripherals_realize()
115 /* Connect DMA 0-6 to the interrupt controller */ in bcm2838_peripherals_realize()
129 /* Connect DMA 7-8 to the interrupt controller */ in bcm2838_peripherals_realize()
146 /* Connect DMA 9-10 to the interrupt controller */ in bcm2838_peripherals_realize()
157 /* Connect DMA 11-14 to the interrupt controller */ in bcm2838_peripherals_realize()
167 * Connect DMA 15 to the interrupt controller, it is physically removed in bcm2838_peripherals_realize()
/qemu/docs/system/
H A Dtarget-mips.rst22 - Core board with MIPS 24Kf CPU and Galileo system controller
24 - PIIX4 PCI/USB/SMbus controller
49 - IDE controller
55 - PC-style IRQ controller
59 - SCSI controller
67 - Bonito64 system controller as North Bridge
77 - LIOINTC as interrupt controller
/qemu/docs/config/
H A Dq35-emulated.cfg30 # 00:1f.2 SATA (AHCI) controller
31 # 00:1f.3 SMBus controller
37 # 00:01.0 VGA compatible controller
38 # 00:19.0 Ethernet controller
39 # 00:1a.* USB controller (#2)
42 # 00:1d.* USB Controller (#1)
129 # An implicit SATA controller is created automatically for
132 # it to that controller so that the guest can use it.
164 # USB controller (#1)
167 # EHCI controller + UHCI companion controllers.
[all …]
H A Dq35-virtio-graphical.cfg30 # 00:1f.2 SATA (AHCI) controller
31 # 00:1f.3 SMBus controller
36 # 00:01.0 VGA compatible controller
39 # 01:00.0 SCSI storage controller
40 # 02:00.0 Ethernet controller
41 # 03:00.0 USB controller
132 # SCSI storage controller (and storage)
175 # Ethernet controller
193 # USB controller (and input devices)
196 # We add a virtualization-friendly USB 3.0 controller and
[all …]
H A Dmach-virt-graphical.cfg33 # 00:01.0 Display controller
35 # 01:00.0 SCSI storage controller
36 # 02:00.0 Ethernet controller
37 # 03:00.0 USB controller
181 # SCSI storage controller (and storage)
224 # Ethernet controller
242 # USB controller (and input devices)
245 # We add a virtualization-friendly USB 3.0 controller and
263 # Display controller
/qemu/hw/i2c/
H A Daspeed_i2c.c2 * ARM Aspeed I2C controller
40 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_raise_interrupt()
76 bus->controller->intr_status |= 1 << bus->id; in aspeed_i2c_bus_raise_interrupt()
83 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_raise_slave_interrupt()
89 bus->controller->intr_status |= 1 << bus->id; in aspeed_i2c_bus_raise_slave_interrupt()
96 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_old_read()
143 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_new_read()
199 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_read()
207 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_set_state()
217 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_get_state()
[all …]
/qemu/include/hw/ppc/
H A Dpnv_xive.h2 * QEMU PowerPC XIVE interrupt controller model
35 /* XSCOM addresses giving access to the controller registers */
74 /* Interrupt controller registers */
99 * XIVE2 interrupt controller (POWER10)
110 /* XSCOM addresses giving access to the controller registers */
135 /* Interrupt controller registers */
/qemu/include/hw/sd/
H A Dallwinner-sdhost.h2 * Allwinner (sun4i and above) SD Host Controller emulation
32 /** Generic Allwinner SD Host Controller (abstract) */
59 * Allwinner SD Host Controller object instance state.
111 uint32_t dmac; /**< Internal DMA Controller Control */
113 uint32_t dmac_status; /**< Internal DMA Controller Status */
114 uint32_t dmac_irq; /**< Internal DMA Controller IRQ Enable */
127 * Allwinner SD Host Controller class-level struct.
H A Dsdhci.h2 * SD Association Host Standard Specification v2.0 controller emulation
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
33 /* SD/MMC host controller state */
83 uint16_t version; /* Host Controller Version Register */
94 /* RO Host Controller Version Register always reads as 0x2401 */
115 * Controller does not provide transfer-complete interrupt when not
/qemu/include/hw/arm/
H A Draspi_platform.h69 #define INTE_OFFSET 0x2000 /* VC Interrupt controller */
74 #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
79 #define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */
123 #define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */
126 #define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */
127 #define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */
129 #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */
/qemu/include/hw/i2c/
H A Daspeed_i2c.h2 * ASPEED AST2400 I2C Controller
247 struct AspeedI2CState *controller; member
314 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_pkt_mode_en()
322 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_ctrl_offset()
330 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_cmd_offset()
338 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_dev_addr_offset()
346 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_intr_ctrl_offset()
354 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_intr_sts_offset()
362 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_pool_ctrl_offset()
370 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_byte_buf_offset()
[all …]
/qemu/hw/intc/
H A Dloongarch_pic_common.c3 * QEMU Loongson 7A1000 I/O interrupt controller.
56 * Interrupt controller identification register 1 in loongarch_pic_common_reset_hold()
57 * Bit 24-31 Interrupt Controller ID in loongarch_pic_common_reset_hold()
58 * Interrupt controller identification register 2 in loongarch_pic_common_reset_hold()
59 * Bit 0-7 Interrupt Controller version number in loongarch_pic_common_reset_hold()

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