Home
last modified time | relevance | path

Searched full:bclk (Results 1 – 25 of 241) sorted by relevance

12345678910

/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dcirrus,lochnagar.yaml95 gf-gpio2, gf-gpio3, gf-gpio7, codec-aif1-bclk,
97 codec-aif2-bclk, codec-aif2-rxdat, codec-aif2-lrclk,
98 codec-aif2-txdat, codec-aif3-bclk, codec-aif3-rxdat,
99 codec-aif3-lrclk, codec-aif3-txdat, dsp-aif1-bclk,
101 dsp-aif2-bclk, dsp-aif2-rxdat, dsp-aif2-lrclk,
102 dsp-aif2-txdat, psia1-bclk, psia1-rxdat, psia1-lrclk,
103 psia1-txdat, psia2-bclk, psia2-rxdat, psia2-lrclk,
104 psia2-txdat, gf-aif3-bclk, gf-aif3-rxdat,
105 gf-aif3-lrclk, gf-aif3-txdat, gf-aif4-bclk,
107 gf-aif1-bclk, gf-aif1-rxdat, gf-aif1-lrclk,
[all …]
/linux-5.10/drivers/media/dvb-frontends/
Dz0194a.h16 u8 bclk = 0; in sharp_z0194a_set_symbol_rate() local
19 aclk = 0xb7; bclk = 0x47; } in sharp_z0194a_set_symbol_rate()
21 aclk = 0xb7; bclk = 0x4b; } in sharp_z0194a_set_symbol_rate()
23 aclk = 0xb7; bclk = 0x4f; } in sharp_z0194a_set_symbol_rate()
25 aclk = 0xb7; bclk = 0x53; } in sharp_z0194a_set_symbol_rate()
27 aclk = 0xb6; bclk = 0x53; } in sharp_z0194a_set_symbol_rate()
29 aclk = 0xb4; bclk = 0x51; } in sharp_z0194a_set_symbol_rate()
32 stv0299_writereg(fe, 0x14, bclk); in sharp_z0194a_set_symbol_rate()
Dbsbe1.h37 u8 bclk = 0; in alps_bsbe1_set_symbol_rate() local
39 if (srate < 1500000) { aclk = 0xb7; bclk = 0x47; } in alps_bsbe1_set_symbol_rate()
40 else if (srate < 3000000) { aclk = 0xb7; bclk = 0x4b; } in alps_bsbe1_set_symbol_rate()
41 else if (srate < 7000000) { aclk = 0xb7; bclk = 0x4f; } in alps_bsbe1_set_symbol_rate()
42 else if (srate < 14000000) { aclk = 0xb7; bclk = 0x53; } in alps_bsbe1_set_symbol_rate()
43 else if (srate < 30000000) { aclk = 0xb6; bclk = 0x53; } in alps_bsbe1_set_symbol_rate()
44 else if (srate < 45000000) { aclk = 0xb4; bclk = 0x51; } in alps_bsbe1_set_symbol_rate()
47 stv0299_writereg(fe, 0x14, bclk); in alps_bsbe1_set_symbol_rate()
Dbsru6.h56 u8 bclk = 0; in alps_bsru6_set_symbol_rate() local
60 bclk = 0x47; in alps_bsru6_set_symbol_rate()
63 bclk = 0x4b; in alps_bsru6_set_symbol_rate()
66 bclk = 0x4f; in alps_bsru6_set_symbol_rate()
69 bclk = 0x53; in alps_bsru6_set_symbol_rate()
72 bclk = 0x53; in alps_bsru6_set_symbol_rate()
75 bclk = 0x51; in alps_bsru6_set_symbol_rate()
79 stv0299_writereg(fe, 0x14, bclk); in alps_bsru6_set_symbol_rate()
/linux-5.10/Documentation/sound/soc/
Ddai.rst15 The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
27 Rx lines are used for audio transmission, while the bit clock (BCLK) and
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
38 MSB is transmitted on the falling edge of the first BCLK after LRC
51 flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
61 MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
Dclocking.rst25 as BCLK). This clock is used to drive the digital audio data across the link
34 - BCLK = MCLK / x, or
35 - BCLK = LRC * x, or
36 - BCLK = LRC * Channels * Word Size
39 it is best to configure BCLK to the lowest possible speed (depending on your
/linux-5.10/drivers/media/pci/mantis/
Dmantis_vp1033.c110 u8 bclk = 0; in lgtdqcs001f_set_symbol_rate() local
114 bclk = 0x47; in lgtdqcs001f_set_symbol_rate()
117 bclk = 0x4b; in lgtdqcs001f_set_symbol_rate()
120 bclk = 0x4f; in lgtdqcs001f_set_symbol_rate()
123 bclk = 0x53; in lgtdqcs001f_set_symbol_rate()
126 bclk = 0x53; in lgtdqcs001f_set_symbol_rate()
129 bclk = 0x51; in lgtdqcs001f_set_symbol_rate()
132 stv0299_writereg(fe, 0x14, bclk); in lgtdqcs001f_set_symbol_rate()
/linux-5.10/sound/soc/samsung/
Dneo1973_wm8753.c28 unsigned int pll_out = 0, bclk = 0; in neo1973_hifi_hw_params() local
40 bclk = WM8753_BCLK_DIV_4; in neo1973_hifi_hw_params()
44 bclk = WM8753_BCLK_DIV_2; in neo1973_hifi_hw_params()
48 bclk = WM8753_BCLK_DIV_16; in neo1973_hifi_hw_params()
52 bclk = WM8753_BCLK_DIV_8; in neo1973_hifi_hw_params()
56 bclk = WM8753_BCLK_DIV_4; in neo1973_hifi_hw_params()
60 bclk = WM8753_BCLK_DIV_2; in neo1973_hifi_hw_params()
77 /* set codec BCLK division for sample rate */ in neo1973_hifi_hw_params()
78 ret = snd_soc_dai_set_clkdiv(codec_dai, WM8753_BCLKDIV, bclk); in neo1973_hifi_hw_params()
/linux-5.10/drivers/staging/greybus/
Daudio_apbridgea.h13 * - the DSP on the MSM8994 is the clock master for MCLK, BCLK, and WCLK
14 * - WCLK changes on the falling edge of BCLK
16 * - TX data is sent on the falling edge of BCLK
17 * - RX data is received/latched on the rising edge of BCLK
/linux-5.10/drivers/gpu/drm/msm/hdmi/
Dhdmi_phy_8996.c128 static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk, in pll_get_integloop_gain() argument
131 int digclk_divsel = bclk >= HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2; in pll_get_integloop_gain()
166 static int pll_get_post_div(struct hdmi_8996_post_divider *pd, u64 bclk) in pll_get_post_div() argument
185 vco = bclk >> half_rate_mode; in pll_get_post_div()
222 u64 bclk; in pll_calculate() local
237 bclk = ((u64)pix_clk) * 10; in pll_calculate()
239 if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) in pll_calculate()
244 ret = pll_get_post_div(&pd, bclk); in pll_calculate()
262 integloop_gain = pll_get_integloop_gain(frac_start, bclk, in pll_calculate()
285 if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD) in pll_calculate()
[all …]
/linux-5.10/sound/soc/codecs/
Dwm9081.c151 int bclk; member
658 * gives us a suitable DAC configuration, plus BCLK. in configure_clock()
664 if (wm9081->master && wm9081->bclk) { in configure_clock()
665 /* Make sure we can generate CLK_SYS and BCLK in configure_clock()
671 if (target >= wm9081->bclk && in configure_clock()
1017 /* If TDM is set up then that fixes our BCLK. */ in wm9081_hw_params()
1021 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots; in wm9081_hw_params()
1023 /* Otherwise work out a BCLK from the sample size */ in wm9081_hw_params()
1024 wm9081->bclk = 2 * wm9081->fs; in wm9081_hw_params()
1028 wm9081->bclk *= 16; in wm9081_hw_params()
[all …]
Dwm8960.c130 int bclk; member
609 * - 10 * bclk = sysclk / bclk_divs
611 * If we cannot find an exact match for (sysclk, lrclk, bclk)
612 * triplet, we relax the bclk such that bclk is chosen as the
613 * closest available frequency greater than expected bclk.
619 * @bclk_idx: bclk_divs index for found bclk
623 * >=0, in case we could derive bclk and lrclk from sysclk using
630 int sysclk, bclk, lrclk; in wm8960_configure_sysclk() local
637 bclk = wm8960->bclk; in wm8960_configure_sysclk()
649 diff = sysclk - bclk * bclk_divs[k] / 10; in wm8960_configure_sysclk()
[all …]
Dda7219.c796 struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX]; in da7219_dai_event() local
805 if (bclk) { in da7219_dai_event()
806 ret = clk_prepare_enable(bclk); in da7219_dai_event()
852 if (bclk) in da7219_dai_event()
853 clk_disable_unprepare(bclk); in da7219_dai_event()
1421 struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX]; in da7219_set_dai_tdm_slot() local
1466 if (bclk) { in da7219_set_dai_tdm_slot()
1469 ret = clk_set_rate(bclk, bclk_rate); in da7219_set_dai_tdm_slot()
1472 "Failed to set TDM BCLK rate %lu: %d\n", in da7219_set_dai_tdm_slot()
1557 struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX]; in da7219_hw_params() local
[all …]
/linux-5.10/Documentation/devicetree/bindings/iommu/
Dmediatek,iommu.txt71 - "bclk": the block clock of m4u.
72 Here is the list which require this "bclk":
75 if there is no this "bclk".
94 clock-names = "bclk";
/linux-5.10/drivers/iio/adc/
Dstm32-adc-core.c81 * @bclk: bus clock common for all ADCs, depends on part used
98 struct clk *bclk; member
206 if (!priv->bclk) { in stm32h7_adc_clk_sel()
241 rate = clk_get_rate(priv->bclk); in stm32h7_adc_clk_sel()
519 if (priv->bclk) { in stm32_adc_core_hw_start()
520 ret = clk_prepare_enable(priv->bclk); in stm32_adc_core_hw_start()
540 if (priv->bclk) in stm32_adc_core_hw_start()
541 clk_disable_unprepare(priv->bclk); in stm32_adc_core_hw_start()
561 if (priv->bclk) in stm32_adc_core_hw_stop()
562 clk_disable_unprepare(priv->bclk); in stm32_adc_core_hw_stop()
[all …]
/linux-5.10/sound/soc/atmel/
Datmel_ssc_dai.h29 #define ATMEL_SSC_CMR_DIV 0 /* MCK divider for BCLK */
30 #define ATMEL_SSC_TCMR_PERIOD 1 /* BCLK divider for transmit FS */
31 #define ATMEL_SSC_RCMR_PERIOD 2 /* BCLK divider for receive FS */
Dmchp-i2s-mcc.c395 unsigned int bclk, unsigned int *mra, in mchp_i2s_mcc_config_divs() argument
407 sysclk = bclk; in mchp_i2s_mcc_config_divs()
413 * BCLK is Selected CLK / (2 * ISCKDIV); in mchp_i2s_mcc_config_divs()
414 * if IMCKDIV or ISCKDIV are 0, MCLK or BCLK = Selected CLK in mchp_i2s_mcc_config_divs()
416 lcm_rate = lcm(sysclk, bclk); in mchp_i2s_mcc_config_divs()
418 (lcm_rate / bclk % 2 == 1 && lcm_rate / bclk > 2)) in mchp_i2s_mcc_config_divs()
423 (clk_rate == bclk || clk_rate / (bclk * 2) <= GENMASK(5, 0)); in mchp_i2s_mcc_config_divs()
467 *mra |= MCHP_I2SMCC_MRA_ISCKDIV(*best_rate / (2 * bclk)); in mchp_i2s_mcc_config_divs()
529 /* cpu is BCLK and LRC master */ in mchp_i2s_mcc_hw_params()
536 /* cpu is BCLK master */ in mchp_i2s_mcc_hw_params()
/linux-5.10/sound/hda/
Dhdac_i915.c20 * snd_hdac_i915_set_bclk - Reprogram BCLK for HSW/BDW
23 * Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
25 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
26 * BCLK = CDCLK * M / N
/linux-5.10/include/sound/sof/
Ddai.h33 #define SOF_DAI_FMT_NB_IF (2 << 8) /**< normal BCLK + inv FRM */
34 #define SOF_DAI_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */
35 #define SOF_DAI_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */
Ddai-imx.h24 uint32_t bclk_rate; /* BCLK frequency in Hz */
45 uint32_t bclk_rate; /* BCLK frequency in Hz */
Ddai-intel.h45 /* bclk keep active */
49 /* bclk idle */
63 uint32_t bclk_rate; /* bclk frequency in Hz */
82 uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK
/linux-5.10/tools/power/cpupower/utils/
Dcpufreq-info.c207 double bclk; in get_boost_mode_x86() local
213 bclk = 100.00; in get_boost_mode_x86()
215 bclk = 133.33; in get_boost_mode_x86()
217 dprint (" Ratio: 0x%llx - bclk: %f\n", in get_boost_mode_x86()
218 intel_turbo_ratio, bclk); in get_boost_mode_x86()
223 ratio * bclk); in get_boost_mode_x86()
228 ratio * bclk); in get_boost_mode_x86()
233 ratio * bclk); in get_boost_mode_x86()
238 ratio * bclk); in get_boost_mode_x86()
/linux-5.10/Documentation/devicetree/bindings/sound/
Dtas2552.txt18 tas2552 can receive its reference clock via MCLK, BCLK, IVCLKIN pin or use the
20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
/linux-5.10/drivers/iommu/
Dmtk_iommu_v1.c482 ret = clk_prepare_enable(data->bclk); in mtk_iommu_hw_init()
484 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); in mtk_iommu_hw_init()
510 clk_disable_unprepare(data->bclk); in mtk_iommu_hw_init()
577 data->bclk = devm_clk_get(dev, "bclk"); in mtk_iommu_probe()
578 if (IS_ERR(data->bclk)) in mtk_iommu_probe()
579 return PTR_ERR(data->bclk); in mtk_iommu_probe()
645 clk_disable_unprepare(data->bclk); in mtk_iommu_remove()
Dmtk_iommu.c114 /* HW will use the EMI clock if there isn't the "bclk". */
556 ret = clk_prepare_enable(data->bclk); in mtk_iommu_hw_init()
558 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); in mtk_iommu_hw_init()
626 clk_disable_unprepare(data->bclk); in mtk_iommu_hw_init()
698 data->bclk = devm_clk_get(dev, "bclk"); in mtk_iommu_probe()
699 if (IS_ERR(data->bclk)) in mtk_iommu_probe()
700 return PTR_ERR(data->bclk); in mtk_iommu_probe()
774 clk_disable_unprepare(data->bclk); in mtk_iommu_remove()
794 clk_disable_unprepare(data->bclk); in mtk_iommu_suspend()
806 ret = clk_prepare_enable(data->bclk); in mtk_iommu_resume()

12345678910