81  * @bclk:		bus clock common for all ADCs, depends on part used
98 	struct clk			*bclk;  member
206 	if (!priv->bclk) {  in stm32h7_adc_clk_sel()
241 	rate = clk_get_rate(priv->bclk);  in stm32h7_adc_clk_sel()
519 	if (priv->bclk) {  in stm32_adc_core_hw_start()
520 		ret = clk_prepare_enable(priv->bclk);  in stm32_adc_core_hw_start()
540 	if (priv->bclk)  in stm32_adc_core_hw_start()
541 		clk_disable_unprepare(priv->bclk);  in stm32_adc_core_hw_start()
561 	if (priv->bclk)  in stm32_adc_core_hw_stop()
562 		clk_disable_unprepare(priv->bclk);  in stm32_adc_core_hw_stop()
672 	priv->bclk = devm_clk_get_optional(&pdev->dev, "bus");  in stm32_adc_probe()
673 	if (IS_ERR(priv->bclk))  in stm32_adc_probe()
674 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk),  in stm32_adc_probe()