| /linux-6.15/arch/sparc/kernel/ |
| D | pci_sun4v.c | 80 return iommu->atu && mask > DMA_BIT_MASK(32); in iommu_use_atu()
119 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num; in iommu_batch_flush()
127 pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n", in iommu_batch_flush()
218 tbl = &iommu->atu->tbl; in dma_4v_alloc_coherent()
328 struct atu *atu; in dma_4v_free_coherent() local
337 atu = iommu->atu; in dma_4v_free_coherent()
344 tbl = &atu->tbl; in dma_4v_free_coherent()
345 iotsb_num = atu->iotsb->iotsb_num; in dma_4v_free_coherent()
361 struct atu *atu; in dma_4v_map_page() local
371 atu = iommu->atu; in dma_4v_map_page()
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| /linux-6.15/drivers/net/dsa/mv88e6xxx/ |
| D | global1_atu.c | 3 * Marvell 88E6xxx Address Translation Unit (ATU) support
18 /* Offset 0x01: ATU FID Register */
25 /* Offset 0x0A: ATU Control Register */
110 /* Offset 0x0B: ATU Operation Register */
144 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ in mv88e6xxx_g1_atu_op()
156 /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ in mv88e6xxx_g1_atu_op()
160 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ in mv88e6xxx_g1_atu_op()
192 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ in mv88e6xxx_g1_atu_fid_read()
200 /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ in mv88e6xxx_g1_atu_fid_read()
204 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ in mv88e6xxx_g1_atu_fid_read()
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| D | global1.h | 44 /* Offset 0x01: ATU FID Register */
112 /* Offset 0x0A: ATU Control Register */
117 /* Offset 0x0B: ATU Operation Register */
134 /* Offset 0x0C: ATU Data Register */
166 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
167 * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
168 * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
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| D | devlink.c | 112 dev_err(chip->dev, "failed to set ATU stats kind/bin\n"); in mv88e6xxx_devlink_atu_bin_get()
118 dev_err(chip->dev, "failed to perform ATU get next\n"); in mv88e6xxx_devlink_atu_bin_get()
124 dev_err(chip->dev, "failed to get ATU stats\n"); in mv88e6xxx_devlink_atu_bin_get()
187 err = dsa_devlink_resource_register(ds, "ATU", in mv88e6xxx_setup_devlink_resources()
304 /* The ATU entry varies between mv88e6xxx chipset generations. Define
669 .name = "atu",
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| /linux-6.15/drivers/pci/controller/dwc/ |
| D | pcie-designware-host.c | 618 struct dw_pcie_ob_atu_cfg atu = { 0 }; in dw_pcie_other_conf_map_bus() local
641 atu.type = type; in dw_pcie_other_conf_map_bus()
642 atu.parent_bus_addr = pp->cfg0_base - pci->parent_bus_offset; in dw_pcie_other_conf_map_bus()
643 atu.pci_addr = busdev; in dw_pcie_other_conf_map_bus()
644 atu.size = pp->cfg0_size; in dw_pcie_other_conf_map_bus()
646 ret = dw_pcie_prog_outbound_atu(pci, &atu); in dw_pcie_other_conf_map_bus()
658 struct dw_pcie_ob_atu_cfg atu = { 0 }; in dw_pcie_rd_other_conf() local
666 atu.type = PCIE_ATU_TYPE_IO; in dw_pcie_rd_other_conf()
667 atu.parent_bus_addr = pp->io_base - pci->parent_bus_offset; in dw_pcie_rd_other_conf()
668 atu.pci_addr = pp->io_bus_addr; in dw_pcie_rd_other_conf()
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| D | pcie-designware.c | 134 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); in dw_pcie_get_resources()
442 dev_err(pci->dev, "Read ATU address failed\n"); in dw_pcie_readl_atu()
462 dev_err(pci->dev, "Write ATU address failed\n"); in dw_pcie_writel_atu()
480 * bit in the Control register-1 of the ATU outbound region acts in dw_pcie_enable_ecrc()
488 * registers, the transactions going through ATU won't have TLP in dw_pcie_enable_ecrc()
518 const struct dw_pcie_ob_atu_cfg *atu) in dw_pcie_prog_outbound_atu() argument
520 u64 parent_bus_addr = atu->parent_bus_addr; in dw_pcie_prog_outbound_atu()
524 limit_addr = parent_bus_addr + atu->size - 1; in dw_pcie_prog_outbound_atu()
528 !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { in dw_pcie_prog_outbound_atu()
532 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, in dw_pcie_prog_outbound_atu()
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| D | pcie-designware-ep.c | 205 struct dw_pcie_ob_atu_cfg *atu) in dw_pcie_ep_outbound_atu() argument
217 atu->index = free_win; in dw_pcie_ep_outbound_atu()
218 ret = dw_pcie_prog_outbound_atu(pci, atu); in dw_pcie_ep_outbound_atu()
223 ep->outbound_addr[free_win] = atu->parent_bus_addr; in dw_pcie_ep_outbound_atu()
502 struct dw_pcie_ob_atu_cfg atu = { 0 }; in dw_pcie_ep_map_addr() local
504 atu.func_no = func_no; in dw_pcie_ep_map_addr()
505 atu.type = PCIE_ATU_TYPE_MEM; in dw_pcie_ep_map_addr()
506 atu.parent_bus_addr = addr - pci->parent_bus_offset; in dw_pcie_ep_map_addr()
507 atu.pci_addr = pci_addr; in dw_pcie_ep_map_addr()
508 atu.size = size; in dw_pcie_ep_map_addr()
[all …]
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| /linux-6.15/arch/sparc/include/asm/ |
| D | iommu_64.h | 30 /* Data structures for SPARC ATU architecture */
46 struct atu { struct
57 struct atu *atu; argument
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| /linux-6.15/Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie-sm8350.yaml | 31 - const: atu # ATU address space
97 reg-names = "parf", "dbi", "elbi", "atu", "config";
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| D | qcom,pcie-sc8180x.yaml | 31 - const: atu # ATU address space
97 "atu",
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| D | fsl,imx6q-pcie-ep.yaml | 76 - const: atu
105 - const: atu
175 reg-names = "dbi", "addr_space", "dbi2", "atu";
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| D | qcom,pcie-sa8775p.yaml | 30 - const: atu # ATU address space
97 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
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| D | qcom,pcie-sm8150.yaml | 31 - const: atu # ATU address space
95 reg-names = "parf", "dbi", "elbi", "atu", "config";
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| D | qcom,pcie-x1e80100.yaml | 30 - const: atu # ATU address space
99 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
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| D | qcom,pcie-sm8250.yaml | 31 - const: atu # ATU address space
108 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
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| D | qcom,pcie-sc8280xp.yaml | 33 - const: atu # ATU address space
113 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
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| D | qcom,pcie-sc7280.yaml | 31 - const: atu # ATU address space
100 reg-names = "parf", "dbi", "elbi", "atu", "config";
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| D | intel,keembay-pcie-ep.yaml | 24 - const: atu
62 reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
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| D | qcom,pcie-sm8550.yaml | 37 - const: atu # ATU address space
108 reg-names = "parf", "dbi", "elbi", "atu", "config";
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| D | qcom,pcie-sm8450.yaml | 33 - const: atu # ATU address space
104 reg-names = "parf", "dbi", "elbi", "atu", "config";
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| D | ti,am65-pci-ep.yaml | 29 - const: atu
70 reg-names = "app", "dbics", "addr_space", "atu";
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| D | host-generic-pci.yaml | 68 DesignWare PCIe controller in RC mode with static ATU window mappings
72 is there any reason for the driver to reconfigure ATU windows for
75 In cases where the IP was synthesized with a minimum ATU window size
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| D | intel,keembay-pcie.yaml | 32 - const: atu
83 reg-names = "dbi", "atu", "config", "apb";
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| D | rcar-gen4-pci-ep.yaml | 32 - const: atu
104 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
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| D | qcom,pcie-ep.yaml | 30 - description: Address Translation Unit (ATU) registers
41 - const: atu
301 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
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