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/qemu/target/i386/hvf/
H A Dx86hvf.c80 if (hv_vcpu_write_fpstate(cs->accel->fd, xsave, xsave_len)) { in hvf_put_xsave()
90 wvmcs(cs->accel->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); in hvf_put_segments()
91 wvmcs(cs->accel->fd, VMCS_GUEST_IDTR_BASE, env->idt.base); in hvf_put_segments()
93 wvmcs(cs->accel->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); in hvf_put_segments()
94 wvmcs(cs->accel->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); in hvf_put_segments()
96 /* wvmcs(cs->accel->fd, VMCS_GUEST_CR2, env->cr[2]); */ in hvf_put_segments()
97 wvmcs(cs->accel->fd, VMCS_GUEST_CR3, env->cr[3]); in hvf_put_segments()
99 wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, env->efer); in hvf_put_segments()
101 macvm_set_cr4(cs->accel->fd, env->cr[4]); in hvf_put_segments()
102 macvm_set_cr0(cs->accel->fd, env->cr[0]); in hvf_put_segments()
[all …]
H A Dhvf.c77 #include "qemu/accel.h"
90 wreg(cpu->accel->fd, HV_X86_TPR, tpr); in vmx_update_tpr()
92 wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0); in vmx_update_tpr()
94 wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : in vmx_update_tpr()
102 int tpr = rreg(cpu->accel->fd, HV_X86_TPR) >> 4; in update_apic_tpr()
220 hv_vcpu_interrupt(&cpu->accel->fd, 1); in hvf_kick_vcpu_thread()
315 wvmcs(cpu->accel->fd, VMCS_PIN_BASED_CTLS, in hvf_arch_init_vcpu()
320 wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, in hvf_arch_init_vcpu()
335 wvmcs(cpu->accel->fd, VMCS_SEC_PROC_BASED_CTLS, in hvf_arch_init_vcpu()
338 wvmcs(cpu->accel->fd, VMCS_ENTRY_CTLS, in hvf_arch_init_vcpu()
[all …]
H A Dx86.c64 base = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_BASE); in x86_read_segment_descriptor()
65 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT); in x86_read_segment_descriptor()
67 base = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_BASE); in x86_read_segment_descriptor()
68 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_LIMIT); in x86_read_segment_descriptor()
87 base = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_BASE); in x86_write_segment_descriptor()
88 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT); in x86_write_segment_descriptor()
90 base = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_BASE); in x86_write_segment_descriptor()
91 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_LIMIT); in x86_write_segment_descriptor()
105 target_ulong base = rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_BASE); in x86_read_call_gate()
106 uint32_t limit = rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_LIMIT); in x86_read_call_gate()
[all …]
H A Dx86_descr.c50 return (uint32_t)rvmcs(cpu->accel->fd, vmx_segment_fields[seg].limit); in vmx_read_segment_limit()
55 return (uint32_t)rvmcs(cpu->accel->fd, vmx_segment_fields[seg].ar_bytes); in vmx_read_segment_ar()
60 return rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base); in vmx_read_segment_base()
66 sel.sel = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector); in vmx_read_segment_selector()
72 wvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector, selector.sel); in vmx_write_segment_selector()
77 desc->sel = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector); in vmx_read_segment_descriptor()
78 desc->base = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base); in vmx_read_segment_descriptor()
79 desc->limit = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].limit); in vmx_read_segment_descriptor()
80 desc->ar = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].ar_bytes); in vmx_read_segment_descriptor()
87 wvmcs(cpu->accel->fd, sf->base, desc->base); in vmx_write_segment_descriptor()
[all …]
H A Dvmx.h183 wreg(cpu->accel->fd, HV_X86_RIP, rip); in macvm_set_rip()
187 val = rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY); in macvm_set_rip()
191 wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, in macvm_set_rip()
203 uint32_t gi = (uint32_t) rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY); in vmx_clear_nmi_blocking()
205 wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); in vmx_clear_nmi_blocking()
214 uint32_t gi = (uint32_t)rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY); in vmx_set_nmi_blocking()
216 wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); in vmx_set_nmi_blocking()
222 val = rvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS); in vmx_set_nmi_window_exiting()
223 wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val | in vmx_set_nmi_window_exiting()
232 val = rvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS); in vmx_clear_nmi_window_exiting()
[all …]
H A Dx86_task.c30 #include "qemu/accel.h"
64 wvmcs(cpu->accel->fd, VMCS_GUEST_CR3, tss->cr3); in load_state_from_tss32()
113 uint64_t rip = rreg(cpu->accel->fd, HV_X86_RIP); in vmx_handle_task_switch()
117 int ins_len = rvmcs(cpu->accel->fd, VMCS_EXIT_INSTRUCTION_LENGTH); in vmx_handle_task_switch()
176 macvm_set_cr0(cpu->accel->fd, rvmcs(cpu->accel->fd, VMCS_GUEST_CR0) | in vmx_handle_task_switch()
183 hv_vcpu_invalidate_tlb(cpu->accel->fd); in vmx_handle_task_switch()
/qemu/accel/
H A Daccel-common.c2 * QEMU accel class, components common to system emulation and user mode
11 #include "qemu/accel.h"
13 #include "accel/accel-cpu.h"
14 #include "accel-internal.h"
39 * The first callback allows accel-cpu to run initializations in accel_init_cpu_int_aux()
42 * The second one allows the CPU to customize the accel-cpu in accel_init_cpu_int_aux()
57 /* initialize the arch-specific accel CpuClass interfaces */
93 AccelState *accel = current_accel(); in accel_cpu_common_realize() local
94 AccelClass *acc = ACCEL_GET_CLASS(accel); in accel_cpu_common_realize()
113 AccelState *accel = current_accel(); in accel_cpu_common_unrealize() local
[all …]
H A Daccel-user.c2 * QEMU accel class, user-mode components
11 #include "qemu/accel.h"
12 #include "accel-internal.h"
21 static AccelState *accel; in current_accel() local
23 if (!accel) { in current_accel()
27 accel = ACCEL(object_new_with_class(OBJECT_CLASS(ac))); in current_accel()
29 return accel; in current_accel()
H A Daccel-system.c2 * QEMU accel class, system emulation components
27 #include "qemu/accel.h"
29 #include "system/accel-ops.h"
32 #include "accel-internal.h"
34 int accel_init_machine(AccelState *accel, MachineState *ms) in accel_init_machine() argument
36 AccelClass *acc = ACCEL_GET_CLASS(accel); in accel_init_machine()
38 ms->accelerator = accel; in accel_init_machine()
44 object_unref(OBJECT(accel)); in accel_init_machine()
58 AccelState *accel = ms->accelerator; in accel_setup_post() local
59 AccelClass *acc = ACCEL_GET_CLASS(accel); in accel_setup_post()
[all …]
H A Dmeson.build1 common_ss.add(files('accel-common.c'))
2 specific_ss.add(files('accel-target.c'))
3 system_ss.add(files('accel-system.c', 'accel-blocker.c'))
4 user_ss.add(files('accel-user.c'))
H A Daccel-target.c2 * QEMU accel class, components common to system emulation and user mode
27 #include "accel/accel-cpu-target.h"
/qemu/host/include/generic/host/crypto/
H A Daes-round.h13 QEMU_ERROR("unsupported accel");
16 QEMU_ERROR("unsupported accel");
19 QEMU_ERROR("unsupported accel");
22 QEMU_ERROR("unsupported accel");
25 QEMU_ERROR("unsupported accel");
28 QEMU_ERROR("unsupported accel");
31 QEMU_ERROR("unsupported accel");
/qemu/docs/devel/migration/
H A Dqpl-compression.rst22 | MultiFD Thread | |accel-config tool |
85 The ``accel-config`` tool is used to enable ``IAA`` devices and configure
90 For ``accel-config`` installation, please refer to `accel-config installation
97 #accel-config config-engine iax1/engine1.0 -g 0
98 #accel-config config-engine iax1/engine1.1 -g 0
99 #accel-config config-engine iax1/engine1.2 -g 0
100 #accel-config config-engine iax1/engine1.3 -g 0
101 #accel-config config-engine iax1/engine1.4 -g 0
102 #accel-config config-engine iax1/engine1.5 -g 0
103 #accel-config config-engine iax1/engine1.6 -g 0
[all …]
/qemu/include/accel/
H A Daccel-cpu-target.h20 * subclasses in target/, or the accel implementation itself in accel/
24 #include "accel/accel-cpu.h"
27 #define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
/qemu/tests/qemu-iotests/tests/
H A Dstream-under-throttle36 Variant of iotests.VM that uses -accel tcg. Simply using
37 iotests.VM.add_args('-accel', 'tcg') is not sufficient, because that will
38 put -accel qtest before -accel tcg, and -accel arguments are prioritized in
43 # Put -accel tcg first so it takes precedence
44 return ['-accel', 'tcg'] + super()._base_args
83 # create an -accel tcg VM
/qemu/include/qemu/
H A Daccel.h45 void (*setup_post)(MachineState *ms, AccelState *accel);
63 #define TYPE_ACCEL "accel"
70 #define ACCEL(obj) \ macro
81 int accel_init_machine(AccelState *accel, MachineState *ms);
88 * @cpu: The CPU that needs to do accel-specific object initializations.
94 * @cpu: The CPU that needs to call accel-specific cpu realization.
101 * @cpu: The CPU that needs to call accel-specific cpu unrealization.
/qemu/accel/hvf/
H A Dhvf-accel-ops.c56 #include "system/accel-ops.h"
204 if (!cpu->accel->dirty) { in do_hvf_cpu_synchronize_state()
206 cpu->accel->dirty = true; in do_hvf_cpu_synchronize_state()
212 if (!cpu->accel->dirty) { in hvf_cpu_synchronize_state()
221 cpu->accel->dirty = true; in do_hvf_cpu_synchronize_set_dirty()
382 hv_return_t ret = hv_vcpu_destroy(cpu->accel->fd); in hvf_vcpu_destroy()
386 g_free(cpu->accel); in hvf_vcpu_destroy()
387 cpu->accel = NULL; in hvf_vcpu_destroy()
394 cpu->accel = g_new0(AccelCPUState, 1); in hvf_init_vcpu()
403 pthread_sigmask(SIG_BLOCK, NULL, &cpu->accel->unblock_ipi_mask); in hvf_init_vcpu()
[all …]
/qemu/accel/tcg/
H A Dmeson.build33 'tcg-accel-ops.c',
34 'tcg-accel-ops-icount.c',
35 'tcg-accel-ops-mttcg.c',
36 'tcg-accel-ops-rr.c',
H A Dmonitor.c10 #include "qemu/accel.h"
45 AccelState *accel = current_accel(); in dump_accel_info() local
46 bool one_insn_per_tb = object_property_get_bool(OBJECT(accel), in dump_accel_info()
161 * otherwise users might think "-accel tcg,tb-size" is not honoured. in dump_exec_info()
207 error_setg(errp, "JIT information is only available with accel=tcg"); in qmp_x_query_jit()
229 "Opcode count information is only available with accel=tcg"); in qmp_x_query_opcount()
/qemu/target/arm/hvf/
H A Dhvf.c558 ret = hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val); in hvf_get_registers()
564 ret = hv_vcpu_get_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg, in hvf_get_registers()
571 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPCR, &val); in hvf_get_registers()
576 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPSR, &val); in hvf_get_registers()
580 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_CPSR, &val); in hvf_get_registers()
589 if (cpu->accel->guest_debug_enabled) { in hvf_get_registers()
675 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, &val); in hvf_get_registers()
698 ret = hv_vcpu_set_reg(cpu->accel->fd, hvf_reg_match[i].reg, val); in hvf_put_registers()
704 ret = hv_vcpu_set_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg, in hvf_put_registers()
709 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPCR, vfp_get_fpcr(env)); in hvf_put_registers()
[all …]
/qemu/docs/specs/
H A Driscv-aia.rst31 chooses to use the irqchip in split mode via "-accel kvm,kernel-irqchip=split",
38 .. list-table:: How AIA and accel options changes controller emulation
42 * - Accel
43 - Accel props
/qemu/system/
H A Drunstate-hmp-cmds.c23 #include "qemu/accel.h"
46 AccelState *accel = current_accel(); in hmp_one_insn_per_tb() local
49 if (!object_property_find(OBJECT(accel), "one-insn-per-tb")) { in hmp_one_insn_per_tb()
64 object_property_set_bool(OBJECT(accel), "one-insn-per-tb", in hmp_one_insn_per_tb()
/qemu/target/i386/nvmm/
H A Dnvmm-all.c14 #include "qemu/accel.h"
25 #include "nvmm-accel-ops.h"
84 AccelCPUState *qcpu = cpu->accel; in nvmm_set_registers()
221 AccelCPUState *qcpu = cpu->accel; in nvmm_get_registers()
344 AccelCPUState *qcpu = cpu->accel; in nvmm_can_take_int()
369 AccelCPUState *qcpu = cpu->accel; in nvmm_can_take_nmi()
392 AccelCPUState *qcpu = cpu->accel; in nvmm_vcpu_pre_run()
475 AccelCPUState *qcpu = cpu->accel; in nvmm_vcpu_post_run()
511 current_cpu->accel->dirty = false; in nvmm_io_callback()
520 current_cpu->accel->dirty = false; in nvmm_mem_callback()
[all …]
/qemu/scripts/
H A Ddevice-crash-test65 # * accel: regexp, full match only
150 # KVM-specific devices shouldn't be tried without accel=kvm:
151 {'accel':'(?!kvm).*', 'device':'kvmclock', 'expected':True},
154 {'accel':'(?!xen).*', 'machine':'xen.*', 'expected':True},
155 {'accel':'(?!xen).*', 'device':'xen-.*', 'expected':True},
207 ('accel' not in rule or
208 'accel' not in t or
209 re.match(rule['accel'] + '$', t['accel'])) and
298 args = ['-S', '-machine', 'none,accel=kvm:tcg']
355 accel = testcase['accel']
[all …]
/qemu/python/qemu/utils/
H A Daccel.py2 QEMU accel module:
39 @raise Exception: if failed to run ``qemu -accel help``
45 out = subprocess.check_output([qemu_bin, '-accel', 'help'],

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