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/qemu/include/libdecnumber/
H A DdecDPD.h67 const uint16_t BCD2DPD[2458]={ 0, 1, 2, 3, 4, 5, 6, 7,
262 const uint16_t DPD2BCD[1024]={ 0, 1, 2, 3, 4, 5, 6, 7,
347 const uint16_t BIN2DPD[1000]={ 0, 1, 2, 3, 4, 5, 6, 7,
430 const uint16_t DPD2BIN[1024]={ 0, 1, 2, 3, 4, 5, 6, 7,
777 '\1','0','0','5', '\1','0','0','6', '\1','0','0','7', '\1','0','0','8', '\1','0','0','9',
779 '\2','0','1','5', '\2','0','1','6', '\2','0','1','7', '\2','0','1','8', '\2','0','1','9',
781 '\2','0','2','5', '\2','0','2','6', '\2','0','2','7', '\2','0','2','8', '\2','0','2','9',
783 '\2','0','3','5', '\2','0','3','6', '\2','0','3','7', '\2','0','3','8', '\2','0','3','9',
785 '\2','0','4','5', '\2','0','4','6', '\2','0','4','7', '\2','0','4','8', '\2','0','4','9',
787 '\2','0','5','5', '\2','0','5','6', '\2','0','5','7', '\2','0','5','8', '\2','0','5','9',
[all …]
H A DdecNumberLocal.h178 #define D2UTABLE {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17, \
184 #define D2UTABLE {0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10, \
189 #define D2UTABLE {0,1,1,1,2,2,2,3,3,3,4,4,4,5,5,5,6,6,6,7,7,7, \
195 6,6,6,7,7,7,7,8,8,8,8,9,9,9,9,10,10,10,10,11, \
200 5,5,5,5,6,6,6,6,6,7,7,7,7,7,8,8,8,8,8,9,9,9, \
205 4,4,4,5,5,5,5,5,5,6,6,6,6,6,6,7,7,7,7,7,7,8, \
207 #elif DECDPUN==7
210 4,4,4,4,4,4,4,5,5,5,5,5,5,5,6,6,6,6,6,6,6,7, \
211 7,7,7,7,7,7}
216 6,6,6,6,6,7}
[all …]
/qemu/tests/tcg/xtensa/
H A Dtest_bi.S6 movi a2, 7
7 beqi a2, 7, 1f
11 beqi a2, 7, 1f
20 bnei a2, 7, 1f
23 movi a2, 7
24 bnei a2, 7, 1f
33 blti a2, 7, 1f
37 blti a2, 7, 1f
40 movi a2, 7
41 blti a2, 7, 1f
[all …]
H A Dtest_clamps.S10 clamps a4, a2, 7
15 clamps a4, a2, 7
20 clamps a4, a2, 7
25 clamps a2, a2, 7
30 clamps a2, a2, 7
35 clamps a2, a2, 7
40 clamps a2, a2, 7
H A Dtest_b.S35 movi a3, 7
43 movi a2, 7
53 movi a3, 7
57 movi a2, 7
154 movi a2, 7
155 movi a3, 7
174 movi a2, 7
175 movi a3, 7
H A Dtest_sext.S10 sext a4, a2, 7
15 sext a4, a2, 7
62 sext a2, a2, 7
67 sext a2, a2, 7
/qemu/target/ppc/translate/
H A Dvmx-ops.c.inc66 GEN_VXFORM(vsl, 2, 7),
68 GEN_VXFORM(vpkuhum, 7, 0),
69 GEN_VXFORM(vpkuwum, 7, 1),
70 GEN_VXFORM_207(vpkudum, 7, 17),
71 GEN_VXFORM(vpkuhus, 7, 2),
72 GEN_VXFORM(vpkuwus, 7, 3),
73 GEN_VXFORM_207(vpkudus, 7, 19),
74 GEN_VXFORM(vpkshus, 7, 4),
75 GEN_VXFORM(vpkswus, 7, 5),
76 GEN_VXFORM_207(vpksdus, 7, 21),
[all …]
/qemu/include/hw/cxl/
H A Dcxl_pci.h43 PCIE_FLEXBUS_PORT_DVSEC = 7,
62 * CXL RCD (D1): 0, [2], [5], 7, [8], A - Not emulated yet
63 * CXL RCD USP (UP1): 7, [8] - Not emulated yet
64 * CXL RCH DSP (DP1): 7, [8]
65 * CXL SLD (D2): 0, [2], 5, 7, 8, [A]
66 * CXL LD (LD): 0, [2], 5, 7, 8
67 * CXL RP (R): 3, 4, 7, 8
68 * CXL Switch USP (USP): [2], 7, 8
69 * CXL Switch DSP (DSP): 3, 4, 7, 8
70 * FM-Owned LD (FMLD): 0, [2], 7, 8, 9
[all …]
/qemu/hw/net/
H A Dtulip.h17 #define CSR0_BLE BIT(7)
39 #define CSR5_RU BIT(7)
50 #define CSR5_RS_MASK 7
52 #define CSR5_TS_MASK 7
60 #define CSR5_TS_RUNNING_CLOSE 7
69 #define CSR5_RS_RUNNING_QUEUE 7
72 #define CSR5_EB_MASK 7
84 #define CSR6_PM BIT(7)
116 #define CSR7_RUM BIT(7)
157 #define CSR12_ANS_MASK 7
[all …]
/qemu/ui/icons/
H A Dqemu.svg222 id="stop3883-7" />
279 xlink:href="#linearGradient3879-4-7"
287 id="linearGradient3879-4-7">
291 id="stop3881-6-7" />
300 id="radialGradient4017-7"
372 xlink:href="#linearGradient3879-4-7-2"
380 id="linearGradient3879-4-7-2">
384 id="stop3881-6-7-9" />
393 id="radialGradient4017-7-9"
414 xlink:href="#linearGradient3879-4-7-2-7"
[all …]
/qemu/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.c41 FIELD(MIO_PIN_0, L3_SEL, 7, 3)
46 FIELD(MIO_PIN_1, L3_SEL, 7, 3)
51 FIELD(MIO_PIN_2, L3_SEL, 7, 3)
56 FIELD(MIO_PIN_3, L3_SEL, 7, 3)
61 FIELD(MIO_PIN_4, L3_SEL, 7, 3)
66 FIELD(MIO_PIN_5, L3_SEL, 7, 3)
71 FIELD(MIO_PIN_6, L3_SEL, 7, 3)
76 FIELD(MIO_PIN_7, L3_SEL, 7, 3)
81 FIELD(MIO_PIN_8, L3_SEL, 7, 3)
86 FIELD(MIO_PIN_9, L3_SEL, 7, 3)
[all …]
/qemu/target/i386/tcg/system/
H A Dbpt_helper.c57 target_ulong dr7 = env->dr[7]; in hw_breakpoint_insert()
71 return hw_breakpoint_enabled(env->dr[7], index) in hw_breakpoint_insert()
102 switch (hw_breakpoint_type(env->dr[7], index)) { in hw_breakpoint_remove()
126 target_ulong old_dr7 = env->dr[7]; in cpu_x86_update_dr7()
145 env->dr[7] = new_dr7; in cpu_x86_update_dr7()
158 env->dr[7] = new_dr7; in cpu_x86_update_dr7()
178 switch (hw_breakpoint_type(env->dr[7], reg)) { in check_hw_breakpoints()
196 if (hw_breakpoint_enabled(env->dr[7], reg)) { in check_hw_breakpoints()
247 if (env->dr[7] & DR7_GD) { in helper_get_dr()
248 env->dr[7] &= ~DR7_GD; in helper_get_dr()
[all …]
/qemu/pc-bios/
H A Dqemu_logo.svg224 id="stop3883-7" />
281 xlink:href="#linearGradient3879-4-7"
289 id="linearGradient3879-4-7">
293 id="stop3881-6-7" />
302 id="radialGradient4017-7"
374 xlink:href="#linearGradient3879-4-7-2"
382 id="linearGradient3879-4-7-2">
386 id="stop3881-6-7-9" />
395 id="radialGradient4017-7-9"
416 xlink:href="#linearGradient3879-4-7-2-7"
[all …]
/qemu/target/mips/
H A Dcpu.h83 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
88 #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \
89 ((v & 0x1f) << 7); \
152 * 7 VPEOpt TCScheFBack TCOpt
155 * Register 4 Register 5 Register 6 Register 7
165 * 7 PWSize
178 * 7 SAAR
191 * 7 GTOffset
204 * 7 Config7 WatchLo7 WatchHi
217 * 7
[all …]
/qemu/tests/unit/
H A Dpkix_asn1_tab.c.inc39 {"encipherOnly", 1073741825, "7"},
125 {0, 4104, "7"},
212 {"privilegeWithdrawn", 1073741825, "7"},
241 {0, 1, "7"},
342 {"pkix", 1, "7"},
407 {0, 1, "7"},
532 {"extnValue", 7, 0},
719 {"pds-name", 1342177283, "7"},
790 {0, 7, 0},
797 {"ia5-terminal", 1073741825, "7"},
[all …]
/qemu/hw/ide/
H A Dahci-internal.h49 #define AHCI_CMD_PREFETCH (1 << 7)
66 AHCI_HOST_REG_EM_LOC = 7, /* EM_LOC: Enclosure Mgmt Location */
123 AHCI_PORT_IRQ_BIT_DMPS = 7,
151 #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
341 * cmd_fis[3], feature 7:0, becomes sector count 7:0.
342 * cmd_fis[7], device 7:0, uses bit 7 as the Force Unit Access bit.
344 * cmd_fis[12], count 7:0, becomes the NCQ TAG (7:3) and RARC bit (0)
345 * cmd_fis[13], count 15:8, becomes the priority value (7:6)
352 uint8_t sector_count_low; /* (feature 7:0) */
356 uint8_t fua; /* (device 7:0) */
[all …]
/qemu/hw/display/
H A Dcirrus_vga_rop2.h65 pattern_y = s->cirrus_blt_srcaddr & 7; in glue()
73 pattern_x = (pattern_x + 1) & 7; in glue()
83 pattern_x = (pattern_x + 1) & 7; in glue()
92 pattern_y = (pattern_y + 1) & 7; in glue()
209 pattern_y = s->cirrus_blt_srcaddr & 7; in glue()
213 bitpos = 7 - srcskipleft; in glue()
220 bitpos = (bitpos - 1) & 7; in glue()
222 pattern_y = (pattern_y + 1) & 7; in glue()
244 pattern_y = s->cirrus_blt_srcaddr & 7; in glue()
248 bitpos = 7 - srcskipleft; in glue()
[all …]
/qemu/tests/tcg/hexagon/
H A Dmisc.c209 asm ("r5 = #7\n\t" in cmpnd_cmp_jump()
212 " p0 = cmp.eq(r5, #7)\n\t" in cmpnd_cmp_jump()
214 " p0 = cmp.eq(r6, #7)\n\t" in cmpnd_cmp_jump()
240 uint32_t init[10] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
446 check32(array[7], 7); in main()
449 S4_storeirbfnew_io(&array[7], false); in main()
471 check32(array[7], 7); in main()
474 S4_storeirhfnew_io(&array[7], false); in main()
496 check32(array[7], 7); in main()
499 S4_storeirifnew_io(&array[7], false); in main()
[all …]
/qemu/linux-user/ppc/
H A Dvdso.S98 .cfi_offset 7, 7 * sizeof_reg
134 .cfi_offset 39, offsetof_mcontext_fregs + 7 * sizeof_freg
172 * DW_CFA_expression reg, length (7),
176 …77 + \reg, 7, 0x23, (offsetof_mcontext_vregs_ptr & 0x7f) + 0x80, offsetof_mcontext_vregs_ptr >> 7,…
193 save_vreg 7
/qemu/include/hw/ppc/
H A Dxive2_regs.h34 #define TM2_QW3W2_LE PPC_BIT32(7)
43 #define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ block# */
63 #define END2_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit */
86 #define END2_W2_RESERVED PPC_BITMASK32(4, 7)
92 #define END2_W4_END_BLOCK PPC_BITMASK32(4, 7)
102 #define END2_W6_VP_BLOCK PPC_BITMASK32(4, 7)
153 #define NVP2_W0_HW PPC_BIT32(7)
165 #define NVP2_W2_CPPR PPC_BITMASK32(0, 7)
174 #define NVP2_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7) /* N:1 */
178 #define NVP2_W5_VP_END_BLOCK PPC_BITMASK32(4, 7)
/qemu/target/openrisc/
H A Dcpu.h53 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
70 UPR_PCUR = (1 << 7),
83 CPUCFGR_OF32S = (1 << 7),
97 DMMUCFGR_NTS = (7 << 2),
98 DMMUCFGR_NAE = (7 << 5),
108 IMMUCFGR_NTS = (7 << 2),
109 IMMUCFGR_NAE = (7 << 5),
122 PMR_SUME = (1 << 7),
133 FPCSR_ZF = (1 << 7),
168 SR_LEE = (1 << 7),
[all …]
/qemu/include/hw/pci-host/
H A Ddino.h10 * https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf
68 #define DINO_IRQ_BUSERRINT 7
80 /* #define xxx 0x080 - bit 7 is "default" */
90 MAKE_64BIT_MASK(0, 7), /* PAMR */
91 MAKE_64BIT_MASK(0, 7), /* PAPR */
93 MAKE_64BIT_MASK(0, 7), /* PCICMD */
/qemu/target/mips/tcg/
H A Dmsa_helper.c111 pwd->b[7] = msa_nloc_df(DF_BYTE, pws->b[7]); in helper_msa_nloc_b()
134 pwd->h[7] = msa_nloc_df(DF_HALF, pws->h[7]); in helper_msa_nloc_h()
169 pwd->b[7] = msa_nlzc_df(DF_BYTE, pws->b[7]); in helper_msa_nlzc_b()
192 pwd->h[7] = msa_nlzc_df(DF_HALF, pws->h[7]); in helper_msa_nlzc_h()
243 pwd->b[7] = msa_pcnt_df(DF_BYTE, pws->b[7]); in helper_msa_pcnt_b()
266 pwd->h[7] = msa_pcnt_df(DF_HALF, pws->h[7]); in helper_msa_pcnt_h()
341 pwd->b[7] = msa_binsl_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]); in helper_msa_binsl_b()
366 pwd->h[7] = msa_binsl_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]); in helper_msa_binsl_h()
422 pwd->b[7] = msa_binsr_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]); in helper_msa_binsr_b()
447 pwd->h[7] = msa_binsr_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]); in helper_msa_binsr_h()
[all …]
/qemu/hw/intc/
H A Di8259.c68 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) { in get_priority()
97 return (priority + s->priority_add) & 7; in pic_get_irq()
161 s->priority_add = (irq + 1) & 7; in pic_intack()
187 irq2 = 7; in pic_read_irq()
198 irq = 7; in pic_read_irq()
266 irq = (priority + s->priority_add) & 7; in pic_ioport_write()
269 s->priority_add = (irq + 1) & 7; in pic_ioport_write()
275 irq = val & 7; in pic_ioport_write()
280 s->priority_add = (val + 1) & 7; in pic_ioport_write()
283 case 7: in pic_ioport_write()
[all …]
/qemu/linux-user/m68k/
H A Dsignal.c87 __put_user(env->aregs[7], &sc->sc_usp); in setup_sigcontext()
101 __get_user(env->aregs[7], &sc->sc_usp); in restore_sigcontext()
154 env->aregs[7] = frame_addr; in setup_frame()
196 __put_user(env->dregs[7], &gregs[7]); in target_rt_setup_ucontext()
204 __put_user(env->aregs[7], &gregs[15]); in target_rt_setup_ucontext()
252 __get_user(env->dregs[7], &gregs[7]); in target_rt_restore_ucontext()
260 __get_user(env->aregs[7], &gregs[15]); in target_rt_restore_ucontext()
317 env->aregs[7] = frame_addr; in setup_rt_frame()
331 abi_ulong frame_addr = env->aregs[7] - 4; in do_sigreturn()
366 abi_ulong frame_addr = env->aregs[7] - 4; in do_rt_sigreturn()

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