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/qemu/target/openrisc/
H A Dinsns.decode50 l_jr 010001 ---------- b:5 -----------
51 l_jalr 010010 ---------- b:5 -----------
58 @load ...... d:5 a:5 i:s16 &load
62 @store ...... ..... a:5 b:5 ........... &store i=%store_i
81 %mtspr_k 21:5 0:11
85 @rri ...... d:5 a:5 i:s16 &rri
86 @rrk ...... d:5 a:5 k:16 &rrk
98 l_mtspr 110000 ..... a:5 b:5 ........... k=%mtspr_k
100 l_maci 010011 ----- a:5 i:s16
102 l_movhi 000110 d:5 ----0 k:16
[all …]
/qemu/include/libdecnumber/
H A DdecDPD.h67 const uint16_t BCD2DPD[2458]={ 0, 1, 2, 3, 4, 5, 6, 7,
262 const uint16_t DPD2BCD[1024]={ 0, 1, 2, 3, 4, 5, 6, 7,
347 const uint16_t BIN2DPD[1000]={ 0, 1, 2, 3, 4, 5, 6, 7,
430 const uint16_t DPD2BIN[1024]={ 0, 1, 2, 3, 4, 5, 6, 7,
777 '\1','0','0','5', '\1','0','0','6', '\1','0','0','7', '\1','0','0','8', '\1','0','0','9',
779 '\2','0','1','5', '\2','0','1','6', '\2','0','1','7', '\2','0','1','8', '\2','0','1','9',
781 '\2','0','2','5', '\2','0','2','6', '\2','0','2','7', '\2','0','2','8', '\2','0','2','9',
783 '\2','0','3','5', '\2','0','3','6', '\2','0','3','7', '\2','0','3','8', '\2','0','3','9',
785 '\2','0','4','5', '\2','0','4','6', '\2','0','4','7', '\2','0','4','8', '\2','0','4','9',
786 '\2','0','5','0', '\2','0','5','1', '\2','0','5','2', '\2','0','5','3', '\2','0','5','4',
[all …]
H A DdecNumberLocal.h143 #define X100(i) (((i)<<2)+((i)<<5)+((i)<<6))
178 #define D2UTABLE {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17, \
184 #define D2UTABLE {0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10, \
189 #define D2UTABLE {0,1,1,1,2,2,2,3,3,3,4,4,4,5,5,5,6,6,6,7,7,7, \
194 #define D2UTABLE {0,1,1,1,1,2,2,2,2,3,3,3,3,4,4,4,4,5,5,5,5,6, \
197 #elif DECDPUN==5
199 #define D2UTABLE {0,1,1,1,1,1,2,2,2,2,2,3,3,3,3,3,4,4,4,4,4,5, \
200 5,5,5,5,6,6,6,6,6,7,7,7,7,7,8,8,8,8,8,9,9,9, \
205 4,4,4,5,5,5,5,5,5,6,6,6,6,6,6,7,7,7,7,7,7,8, \
210 4,4,4,4,4,4,4,5,5,5,5,5,5,5,6,6,6,6,6,6,6,7, \
[all …]
/qemu/target/hppa/
H A Dinsns.decode31 %assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2
35 %assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11
41 %rm64 1:1 16:5
42 %rt64 6:1 0:5
43 %ra64 7:1 21:5
44 %rb64 12:1 16:5
50 %len5 0:5 !function=assemble_6
51 %len6_8 8:1 0:5 !function=assemble_6
52 %len6_12 12:1 0:5 !function=assemble_6
53 %cpos6_11 11:1 5:5
[all …]
/qemu/target/avr/
H A Dinsn.decode26 %rd 4:5
66 COM 1001 010 rd:5 0000
67 NEG 1001 010 rd:5 0001
68 INC 1001 010 rd:5 0011
69 DEC 1001 010 rd:5 1010
85 %imm_call 4:5 0:1 !function=append_16
104 SBRC 1111 110 rr:5 0 bit:3
105 SBRS 1111 111 rr:5 0 bit:3
106 SBIC 1001 1001 reg:5 bit:3
107 SBIS 1001 1011 reg:5 bit:3
[all …]
/qemu/target/mips/tcg/
H A Docteon.decode14 %bbit_p 28:1 16:5
15 BBIT 11 set:1 . 10 rs:5 ..... offset:s16 p=%bbit_p
31 @r3 ...... rs:5 rt:5 rd:5 ..... ......
32 %bitfield_p 0:1 6:5
33 @bitfield ...... rs:5 rt:5 lenm1:5 ..... ..... . p=%bitfield_p
39 POP 011100 rs:5 00000 rd:5 00000 10110 dw:1
40 SEQNE 011100 rs:5 rt:5 rd:5 00000 10101 ne:1
41 SEQNEI 011100 rs:5 rt:5 imm:s10 10111 ne:1
H A Dmsa.decode32 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
33 @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i
34 @bz_v ...... ... .. wt:5 sa:s16 &msa_bz df=3
35 @bz ...... ... df:2 wt:5 sa:s16 &msa_bz
36 @elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df=%elm_df n=%elm_n
37 @elm ...... .......... ws:5 wd:5 ...... &msa_elm
38 @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
39 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
40 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w
41 @3r ...... ... df:2 wt:5 ws:5 wd:5 ...... &msa_r
[all …]
/qemu/target/ppc/
H A Dinternal.h101 EXTRACT_HELPER(opc2, 1, 5);
103 EXTRACT_HELPER(opc3, 6, 5);
105 EXTRACT_HELPER(opc4, 16, 5);
111 EXTRACT_HELPER(rD, 21, 5);
113 EXTRACT_HELPER(rS, 21, 5);
115 EXTRACT_HELPER(rA, 16, 5);
117 EXTRACT_HELPER(rB, 11, 5);
119 EXTRACT_HELPER(rC, 6, 5);
124 EXTRACT_HELPER(crbD, 21, 5);
125 EXTRACT_HELPER(crbA, 16, 5);
[all …]
H A Dinsn32.decode21 @A ...... frt:5 fra:5 frb:5 frc:5 ..... rc:1 &A
24 @A_tab ...... frt:5 fra:5 frb:5 ..... ..... rc:1 &A_tab
27 @A_tac ...... frt:5 fra:5 ..... frc:5 ..... rc:1 &A_tac
30 @A_tb ...... frt:5 ..... frb:5 ..... ..... rc:1 &A_tb
33 @A_tab_bc ...... rt:5 ra:5 rb:5 bc:5 ..... . &A_tab_bc
36 @D ...... rt:5 ra:5 si:s16 &D
39 @D_ui ...... rt:5 ra:5 ui:16 &D_ui
42 @D_bfs ...... bf:3 . l:1 ra:5 imm:s16 &D_bf
43 @D_bfu ...... bf:3 . l:1 ra:5 imm:16 &D_bf
47 @DQ_rtp ...... ....0 ra:5 ............ .... &D rt=%dq_rtp si=%dq_si
[all …]
/qemu/target/arm/tcg/
H A Da64.decode22 %rd 0:5
48 @rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1
49 @rr_s ........ ... ..... ...... rn:5 rd:5 &rr_e esz=2
50 @rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3
51 @rr_e ........ esz:2 . ..... ...... rn:5 rd:5 &rr_e
52 @rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd
53 @rr_hsd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_hsd
55 @rrr_b ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=0
56 @rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1
57 @rrr_s ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=2
[all …]
H A Dsve.decode26 %imm6_22_5 22:1 5:5
27 %imm7_22_16 22:2 16:5
28 %imm8_16_10 16:5 10:3
37 %tszimm_esz 22:2 5:5 !function=tszimm_esz
39 %tszimm_shr 22:2 5:5 !function=tszimm_shr
41 %tszimm_shl 22:2 5:5 !function=tszimm_shl
44 %tszimm16_esz 22:2 16:5 !function=tszimm_esz
45 %tszimm16_shr 22:2 16:5 !function=tszimm_shr
46 %tszimm16_shl 22:2 16:5 !function=tszimm_shl
49 %sh8_i8s 5:9 !function=expand_imm_sh8s
[all …]
H A Dsme.decode31 MOVA 11000000 esz:2 00000 0 v:1 .. pg:3 zr:5 0 za_imm:4 \
33 MOVA 11000000 11 00000 1 v:1 .. pg:3 zr:5 0 za_imm:4 \
36 MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5 \
38 MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \
45 LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \
47 LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \
51 @ldstr ....... ... . ...... .. ... rn:5 . imm:4 \
60 @adda_32 ........ .. ..... . pm:3 pn:3 zn:5 ... zad:2 &adda
61 @adda_64 ........ .. ..... . pm:3 pn:3 zn:5 .. zad:3 &adda
71 @op_32 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 .. zad:2 &op
[all …]
/qemu/target/sparc/
H A Dinsns.decode17 BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16
21 SETHI 00 rd:5 100 i:22
29 %dfp_rd 25:5 !function=extract_dfpreg
30 %dfp_rs1 14:5 !function=extract_dfpreg
31 %dfp_rs2 0:5 !function=extract_dfpreg
32 %dfp_rs3 9:5 !function=extract_dfpreg
34 %qfp_rd 25:5 !function=extract_qfpreg
35 %qfp_rs1 14:5 !function=extract_qfpreg
36 %qfp_rs2 0:5 !function=extract_qfpreg
39 @n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0
[all …]
/qemu/tests/tcg/xtensa/
H A Dtest_loop.S9 movi a3, 5
13 assert eqi, a2, 5
27 movi a3, 5
37 movi a3, 5
47 movi a3, 5
64 movi a3, 5
101 assert eqi, a2, 5
106 movi a3, 5
131 movi a3, 5
135 assert eqi, a2, 5
[all …]
/qemu/linux-user/mips/
H A Dsyscall-args-o32.c.inc6 [ 5] = 3, /* open */
22 [ 21] = 5, /* mount */
114 [ 113] = 5, /* vm86 */
121 [ 120] = 5, /* clone */
141 [ 140] = 5, /* _llseek */
143 [ 142] = 5, /* _newselect */
168 [ 167] = 5, /* mremap */
174 [ 173] = 5, /* getsockopt */
182 [ 181] = 5, /* setsockopt */
188 [ 187] = 5, /* query_module */
[all …]
/qemu/target/ppc/translate/
H A Dvmx-ops.c.inc40 GEN_VXFORM(vmrglh, 6, 5),
75 GEN_VXFORM(vpkswus, 7, 5),
86 GEN_VXFORM(vaddfp, 5, 0),
87 GEN_VXFORM(vsubfp, 5, 1),
88 GEN_VXFORM(vmaxfp, 5, 16),
89 GEN_VXFORM(vminfp, 5, 17),
137 GEN_VXFORM_NOA(vrefp, 5, 4),
138 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
139 GEN_VXFORM_NOA(vexptefp, 5, 6),
140 GEN_VXFORM_NOA(vlogefp, 5, 7),
[all …]
/qemu/tests/unit/
H A Dtest-x86-topo.c66 g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 5); in test_topo_bits()
70 g_assert_cmpuint(apicid_core_width(&topo_info), ==, 5); in test_topo_bits()
72 g_assert_cmpuint(apicid_core_width(&topo_info), ==, 5); in test_topo_bits()
74 g_assert_cmpuint(apicid_core_width(&topo_info), ==, 5); in test_topo_bits()
104 g_assert_cmpuint(apicid_module_offset(&topo_info), ==, 5); in test_topo_bits()
105 g_assert_cmpuint(apicid_die_offset(&topo_info), ==, 5); in test_topo_bits()
106 g_assert_cmpuint(apicid_pkg_offset(&topo_info), ==, 5); in test_topo_bits()
128 g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 5 * 3 + 0), ==, in test_topo_bits()
129 (5 << 2) | 0); in test_topo_bits()
130 g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 5 * 3 + 1), ==, in test_topo_bits()
[all …]
/qemu/target/microblaze/
H A Dinsns.decode32 @typea ...... rd:5 ra:5 rb:5 ... .... .... &typea
33 @typeb ...... rd:5 ra:5 ................ &typeb imm=%extimm
36 @typea0 ...... rd:5 ra:5 ................ &typea0
39 @typea_br ...... rd:5 ..... rb:5 ........... &typea_br
42 @typea_bc ...... ..... ra:5 rb:5 ........... &typea_bc
45 @typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb
48 @typeb_br ...... rd:5 ..... ................ &typeb_br imm=%extimm
51 @typeb_bc ...... ..... ra:5 ................ &typeb_bc imm=%extimm
55 # match the required zero at bit 5.
56 %ieimm 6:5 0:5
[all …]
/qemu/tests/functional/
H A Dtest_mips64el_replay.py16 'linux-image-2.6.32-5-5kc-malta_2.6.32-48_mipsel.deb'),
22 member='boot/vmlinux-2.6.32-5-5kc-malta')
25 self.run_rr(kernel_path, kernel_command_line, console_pattern, shift=5)
43 self.cpu = '5KEc'
51 self.run_rr(kernel_path, kernel_command_line, console_pattern, shift=5,
/qemu/target/riscv/
H A Dinstmap.h303 | (extract32(inst, 25, 6) << 5) \
307 #define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \
308 | (sextract64(inst, 25, 7) << 5))
318 #define GET_RS3(inst) extract32(inst, 27, 5)
319 #define GET_RS1(inst) extract32(inst, 15, 5)
320 #define GET_RS2(inst) extract32(inst, 20, 5)
321 #define GET_RD(inst) extract32(inst, 7, 5)
323 #define SET_RS1(inst, val) deposit32(inst, 15, 5, val)
324 #define SET_RS2(inst, val) deposit32(inst, 20, 5, val)
325 #define SET_RD(inst, val) deposit32(inst, 7, 5, val)
[all …]
/qemu/target/mips/
H A Dcpu.h130 #define MIPS_TC_MAX 5
150 * 5 VPESchedule TCContext
155 * Register 4 Register 5 Register 6 Register 7
163 * 5 MemoryMapID PWBase SRSConf4
176 * 5 GuestCtl2
189 * 5 SRSMap2 NestedExc
202 * 5 Config5 WatchLo5 WatchHi
215 * 5 TraceDBPC
228 * 5 PerfCnt
241 * 5 TagLo2 TagHi2 KScratch<n>
[all …]
/qemu/include/ui/
H A Dpixel_ops.h4 return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6); in rgb_to_pixel8()
10 return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3); in rgb_to_pixel15()
16 return ((b >> 3) << 10) | ((g >> 3) << 5) | (r >> 3); in rgb_to_pixel15bgr()
22 return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3); in rgb_to_pixel16()
28 return ((b >> 3) << 11) | ((g >> 2) << 5) | (r >> 3); in rgb_to_pixel16bgr()
/qemu/tests/qemu-iotests/
H A D026.out6 Event: l1_update; errno: 5; imm: off; once: on; write
11 Event: l1_update; errno: 5; imm: off; once: on; write -b
16 Event: l1_update; errno: 5; imm: off; once: off; write
23 Event: l1_update; errno: 5; imm: off; once: off; write -b
54 Event: l2_load; errno: 5; imm: off; once: on; write
62 Event: l2_load; errno: 5; imm: off; once: on; write -b
70 Event: l2_load; errno: 5; imm: off; once: off; write
78 Event: l2_load; errno: 5; imm: off; once: off; write -b
118 Event: l2_update; errno: 5; imm: off; once: on; write
123 Event: l2_update; errno: 5; imm: off; once: on; write -b
[all …]
H A D026.out.nocache6 Event: l1_update; errno: 5; imm: off; once: on; write
11 Event: l1_update; errno: 5; imm: off; once: on; write -b
16 Event: l1_update; errno: 5; imm: off; once: off; write
23 Event: l1_update; errno: 5; imm: off; once: off; write -b
54 Event: l2_load; errno: 5; imm: off; once: on; write
62 Event: l2_load; errno: 5; imm: off; once: on; write -b
70 Event: l2_load; errno: 5; imm: off; once: off; write
78 Event: l2_load; errno: 5; imm: off; once: off; write -b
118 Event: l2_update; errno: 5; imm: off; once: on; write
124 Event: l2_update; errno: 5; imm: off; once: on; write -b
[all …]
/qemu/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.c42 FIELD(MIO_PIN_0, L2_SEL, 5, 2)
47 FIELD(MIO_PIN_1, L2_SEL, 5, 2)
52 FIELD(MIO_PIN_2, L2_SEL, 5, 2)
57 FIELD(MIO_PIN_3, L2_SEL, 5, 2)
62 FIELD(MIO_PIN_4, L2_SEL, 5, 2)
67 FIELD(MIO_PIN_5, L2_SEL, 5, 2)
72 FIELD(MIO_PIN_6, L2_SEL, 5, 2)
77 FIELD(MIO_PIN_7, L2_SEL, 5, 2)
82 FIELD(MIO_PIN_8, L2_SEL, 5, 2)
87 FIELD(MIO_PIN_9, L2_SEL, 5, 2)
[all …]

12345678910>>...77