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/qemu/ui/
H A Dvnc-enc-zywrle.h101 48, 48, 48, 48, 48, 48, 48, 48,
102 48, 48, 48, 56, 56, 56, 56, 56,
121 -56, -56, -56, -56, -56, -56, -48, -48,
122 -48, -48, -48, -48, -48, -48, -48, -48,
123 -48, -32, -32, -32, -32, -32, -32, -32,
134 48, 48, 48, 48, 48, 48, 48, 48,
135 48, 48, 48, 48, 48, 48, 48, 48,
136 48, 48, 48, 48, 48, 48, 48, 48,
155 -64, -48, -48, -48, -48, -48, -48, -48,
156 -48, -48, -48, -48, -48, -48, -48, -48,
[all …]
/qemu/target/arm/tcg/
H A Diwmmxt_helper.c64 EXTEND16S((a >> 48) & 0xffff) * EXTEND16S((b >> 48) & 0xffff) in HELPER()
76 ((a >> 48) & 0xffff) * ((b >> 48) & 0xffff) in HELPER()
87 SADB(32) + SADB(40) + SADB(48) + SADB(56); in HELPER()
95 return SADW(0) + SADW(16) + SADW(32) + SADW(48); in HELPER()
104 return MULS(0) | MULS(16) | MULS(32) | MULS(48); in HELPER()
113 return MULS(0) | MULS(16) | MULS(32) | MULS(48); in HELPER()
122 return MULU(0) | MULU(16) | MULU(32) | MULU(48); in HELPER()
131 return MULU(0) | MULU(16) | MULU(32) | MULU(48); in HELPER()
139 return (int64_t) (MACS(0) + MACS(16) + MACS(32) + MACS(48)); in HELPER()
148 return MACU(0) + MACU(16) + MACU(32) + MACU(48); in HELPER()
[all …]
H A Dneon_helper.c642 SAT8(48); in HELPER()
666 SAT8(48); in HELPER()
690 SAT8(48); in HELPER()
799 ret |= tmp << 48; in HELPER()
813 ret |= tmp << 48; in HELPER()
867 reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48); in HELPER()
926 result |= tmp << 48; in HELPER()
940 result |= tmp << 48; in HELPER()
995 result |= tmp << 48; in HELPER()
1010 result |= tmp << 48; in HELPER()
[all …]
H A Dpauth_helper.c40 o |= extract64(i, 48, 4) << 20; in pac_cell_shuffle()
49 o |= extract64(i, 8, 4) << 48; in pac_cell_shuffle()
63 o |= extract64(i, 48, 4) << 8; in pac_cell_inv_shuffle()
76 o |= extract64(i, 20, 4) << 48; in pac_cell_inv_shuffle()
181 o |= extract64(i, 48, 4) << 32; in tweak_shuffle()
186 o |= tweak_cell_rot(extract64(i, 0, 4)) << 48; in tweak_shuffle()
203 o |= tweak_cell_inv_rot(extract64(i, 48, 4)); in tweak_inv_shuffle()
218 o |= extract64(i, 32, 4) << 48; in tweak_inv_shuffle()
/qemu/tests/qemu-iotests/
H A D125.out130 --- cluster_size=512 growth_size=48 create_mode=off growth_mode=off ---
136 48 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
138 --- cluster_size=512 growth_size=48 create_mode=off growth_mode=metadata ---
144 48 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
146 --- cluster_size=512 growth_size=48 create_mode=off growth_mode=falloc ---
152 48 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
154 --- cluster_size=512 growth_size=48 create_mode=off growth_mode=full ---
160 48 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
162 --- cluster_size=512 growth_size=48 create_mode=metadata growth_mode=off ---
168 48 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D125106 # Therefore, we create an image that is 48 kB below 2 MB. Then:
108 # (2) We resize it to 2 MB. (+ 48 kB)
112 CREATION_SIZE=$((2 * 1024 * 1024 - 48 * 1024))
117 for GROWTH_SIZE in 16 48 80; do
/qemu/hw/ide/
H A Dide-internal.h75 #define WIN_READ_EXT 0x24 /* 48-Bit */
76 #define WIN_READDMA_EXT 0x25 /* 48-Bit */
77 #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit, obsolete since ACS2 */
78 #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
80 #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
88 #define WIN_WRITE_EXT 0x34 /* 48-Bit */
89 #define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
90 #define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
91 #define WIN_SET_MAX_EXT 0x37 /* 48-Bit, obsolete since ACS2 */
92 #define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
[all …]
/qemu/linux-user/aarch64/
H A Dtarget_mman.h13 * VA_BITS_MIN 48 (unless explicitly configured smaller)
15 #define TASK_UNMAPPED_BASE (1ull << (48 - 2))
18 #define ELF_ET_DYN_BASE TARGET_PAGE_ALIGN((1ull << 48) / 3 * 2)
/qemu/common-user/host/s390x/
H A Dsafe-syscall.inc.S26 stmg %r6,%r15,48(%r15) /* save all call-saved registers */
28 .cfi_offset %r14,-48
81 lmg %r6,%r15,48(%r15) /* load saved registers */
93 lmg %r6,%r15,48(%r15) /* load saved registers */
/qemu/target/loongarch/
H A Dcpu-param.h11 #define TARGET_PHYS_ADDR_SPACE_BITS 48
12 #define TARGET_VIRT_ADDR_SPACE_BITS 48
/qemu/target/mips/
H A Dcpu-param.h11 #define TARGET_PHYS_ADDR_SPACE_BITS 48
12 #define TARGET_VIRT_ADDR_SPACE_BITS 48
/qemu/target/sparc/
H A Dcpu.c215 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
224 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
233 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
242 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
251 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
260 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
269 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
278 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
287 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
296 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
[all …]
/qemu/target/i386/
H A Dcpu-param.h14 * ??? This is really 48 bits, sign-extended, but the only thing
15 * accessible to userland with bit 48 set is the VSYSCALL, and that
H A Dmonitor.c44 addr |= (hwaddr)-(1LL << 48); in addr_canonical()
163 print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30), in tlb_info_la48()
178 print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30) + in tlb_info_la48()
190 print_pte(mon, env, (l0 << 48) + (l1 << 39) + in tlb_info_la48()
449 mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 48, 0); in mem_info_la48()
465 end = l0 << 48; in mem_info_la57()
476 end = (l0 << 48) + (l1 << 39); in mem_info_la57()
487 end = (l0 << 48) + (l1 << 39) + (l2 << 30); in mem_info_la57()
506 end = (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21); in mem_info_la57()
525 end = (l0 << 48) + (l1 << 39) + (l2 << 30) + in mem_info_la57()
/qemu/tests/tcg/alpha/
H A Dtest-cvttq.c22 #define FPCR_DNZ (1UL << 48)
73 T[i].d, T[i].r, T[i].e >> 48, r, e >> 48); in main()
/qemu/tests/tcg/aarch64/
H A Dpauth-2.c27 * With TBI enabled and a 48-bit VA, there are 7 bits of auth, in do_test()
71 assert(((decode >> 48) & 0xff) == 0b10111111); in do_test()
73 assert(((decode >> 48) & 0xff) == 0b00100000); in do_test()
H A Dsme-outprod1.c18 " stp d12, d13, [sp, 48]\n"
51 " ldp d12, d13, [sp, 48]\n"
/qemu/target/alpha/
H A Dvax_helper.c90 r |= (a & 0xc000000000000000ull) >> 48; in helper_f_to_memory()
97 r = ((uint64_t)(a & 0x0000c000)) << 48; in helper_memory_to_f()
219 r = (a & 0x000000000000ffffull) << 48; in helper_g_to_memory()
222 r |= (a & 0xffff000000000000ull) >> 48; in helper_g_to_memory()
229 r = (a & 0x000000000000ffffull) << 48; in helper_memory_to_g()
232 r |= (a & 0xffff000000000000ull) >> 48; in helper_memory_to_g()
/qemu/hw/char/
H A Driscv_htif.c38 #define HTIF_CMD_SHIFT 48
106 s->fromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); in htif_recv()
132 * Bits 55:48 indicate the "command".
258 s->fromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); in htif_handle_tohost_write()
/qemu/include/hw/pci-host/
H A Dpnv_phb4_regs.h462 #define IODA3_MIST_P3 PPC_BIT(48 + 0)
463 #define IODA3_MIST_Q3 PPC_BIT(48 + 1)
464 #define IODA3_MIST_PE3 PPC_BITMASK(48 + 4, 48 + 15)
468 #define IODA3_TVT_NUM_LEVELS PPC_BITMASK(48, 50)
493 #define IODA3_MDT_PE_D PPC_BITMASK(48, 63)
553 #define IODA3_PEST0_MSI_DATA PPC_BITMASK(48, 63)
H A Dpnv_phb3_regs.h77 #define PHB_IVT_BASE_ADDRESS_MASK PPC_BITMASK(14, 48)
141 #define PHB_IVC_UPDATE_SID PPC_BITMASK(48, 63)
360 #define IODA2_IVT_PE PPC_BITMASK(48, 63)
364 #define IODA2_TVT_NUM_LEVELS PPC_BITMASK(48, 50)
429 #define IODA2_PEST0_MSI_DATA PPC_BITMASK(48, 63)
/qemu/target/xtensa/core-test_kc705_be/
H A Dgdb-config.c.inc35 XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
71 XTREG( 48,192,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
76 XTREG( 53,212,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0,
77 "03:40:48:2b","03:40:48:7a",0,0,0,0)
78 XTREG( 54,220,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1,
80 XTREG( 55,228,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2,
82 XTREG( 56,236,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3,
84 XTREG( 57,244,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4,
86 XTREG( 58,252,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5,
88 XTREG( 59,260,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6,
[all …]
/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dgdb-config.c.inc35 XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
69 XTREG( 46,184,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0,
71 XTREG( 47,192,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1,
73 XTREG( 48,200,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2,
75 XTREG( 49,208,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3,
77 XTREG( 50,216,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4,
79 XTREG( 51,224,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5,
81 XTREG( 52,232,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6,
83 XTREG( 53,240,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7,
/qemu/tests/functional/
H A Dtest_mips64el_malta.py27 'linux-image-2.6.32-5-5kc-malta_2.6.32-48_mipsel.deb'),
38 [1] http://snapshot.debian.org/package/linux-2.6/2.6.32-48/
39 #linux-source-2.6.32_2.6.32-48
/qemu/hw/tricore/
H A Dtricore_testboard.c76 memory_region_init_ram(int_cram, NULL, "powerlink_int_c.ram", 48 * KiB, in tricore_testboard_init()
78 memory_region_init_ram(int_dram, NULL, "powerlink_int_d.ram", 48 * KiB, in tricore_testboard_init()

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