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/linux-5.10/Documentation/devicetree/bindings/timer/
Drenesas,cmt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
26 - items:
27 - enum:
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
[all …]
/linux-5.10/drivers/gpio/
Dgpio-104-idi-48.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-IDI-48 family
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
30 MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
34 MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
37 * struct idi_48_gpio - GPIO device private data structure
43 * @cos_enb: Change-Of-State IRQ enable boundaries mask
72 for (i = 0; i < 48; i += 8) in idi_48_gpio_get()
75 mask = BIT(offset - i); in idi_48_gpio_get()
[all …]
Dgpio-104-dio-48e.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-DIO-48E series
6 * This driver supports the following ACCES devices: 104-DIO-48E and
7 * 104-DIO-24E.
30 MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
34 MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
37 * struct dio48e_gpio - GPIO device private data structure
39 * @io_state: bit I/O state (whether bit is set to input or output)
60 const unsigned mask = BIT(offset % 8); in dio48e_gpio_get_direction()
62 if (dio48egpio->io_state[port] & mask) in dio48e_gpio_get_direction()
[all …]
/linux-5.10/Documentation/arm64/
Dmemory.rst12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
21 User addresses have bits 63:48 set to 0 while the kernel addresses have
22 the same bits set to 1. TTBRx selection is given by bit 63 of the
24 mappings while the user pgd contains only user (non-global) mappings.
29 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
32 -----------------------------------------------------------------------
48 AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
51 -----------------------------------------------------------------------
70 +--------+--------+--------+--------+--------+--------+--------+--------+
[all …]
/linux-5.10/include/uapi/linux/
Ddccp.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
9 * struct dccp_hdr - generic part of DCCP packet header
11 * @dccph_sport - Relevant port on the endpoint that sent this packet
12 * @dccph_dport - Relevant port on the other endpoint
13 * @dccph_doff - Data Offset from the start of the DCCP header, in 32-bit words
14 * @dccph_ccval - Used by the HC-Sender CCID
15 * @dccph_cscov - Parts of the packet that are covered by the Checksum field
16 * @dccph_checksum - Internet checksum, depends on dccph_cscov
17 * @dccph_x - 0 = 24 bit sequence number, 1 = 48
18 * @dccph_type - packet type, see DCCP_PKT_ prefixed macros
[all …]
Dhdreg.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
17 #define IDE_DRIVE_TASK_INVALID -1
137 * 0x01->0x02 Reserved
141 * 0x04->0x07 Reserved
146 * 0x09->0x0F Reserved
151 * 0x10->0x1F Reserved
153 #define WIN_READ 0x20 /* 28-Bit */
154 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
155 #define WIN_READ_LONG 0x22 /* 28-Bit */
156 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
[all …]
/linux-5.10/Documentation/core-api/
Dpacking.rst6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
[all …]
/linux-5.10/arch/mips/include/asm/sgi/
Dheart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
7 * 2007-2015 Joshua Kinard <kumba@gentoo.org>
27 * struct ip30_heart_regs - struct that maps IP30 HEART registers.
28 * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
29 * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
30 * @mem_refresh: HEART_MEM_REF - purpose unknown.
31 * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
32 * @mem_cfg.q: union for 64bit access to HEART_MEMCFG - 4x 64bit registers.
33 * @mem_cfg.l: union for 32bit access to HEART_MEMCFG - 8x 32bit registers.
[all …]
/linux-5.10/Documentation/sound/cards/
Daudiophile-usb.rst2 Guide to using M-Audio Audiophile USB with ALSA and Jack
9 This document is a guide to using the M-Audio Audiophile USB (tm) device with
15 * v1.4 - Thibault Le Meur (2007-07-11)
17 - Added Low Endianness nature of 16bits-modes
19 - Modifying document structure
21 * v1.5 - Thibault Le Meur (2007-07-12)
22 - Added AC3/DTS passthru info
35 - This port supports 2 pairs of line-level audio inputs (1/4" TS and RCA)
36 - When the 1/4" TS (jack) connectors are connected, the RCA connectors
52 Please exit any audio application running before switching between bit depths
[all …]
/linux-5.10/arch/powerpc/kernel/vdso32/
Dsigtramp.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
23 .Lsig_start = . - 4
43 .uleb128 9f - 1f; /* length */ \
56 .uleb128 9f - 1f; /* length */ \
65 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
72 .uleb128 9f - 1f; /* length */ \
97 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
102 .uleb128 9f - 1f; /* length */ \
105 .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
108 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
[all …]
/linux-5.10/drivers/staging/media/hantro/
Dimx8m_vpu_hw.c1 // SPDX-License-Identifier: GPL-2.0
16 #define RESET_G1 BIT(1)
17 #define RESET_G2 BIT(0)
20 #define CLOCK_G1 BIT(1)
21 #define CLOCK_G2 BIT(0)
32 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
34 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
39 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
41 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
48 val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
[all …]
/linux-5.10/arch/x86/crypto/
Dcrct10dif-pcl-asm_64.S2 # Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
50 # /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
107 # bit order match the polynomial coefficient order.
137 # While >= 128 data bytes remain (not counting xmm0-7), fold the 128
138 # bytes xmm0-7 into them, storing the result back into xmm0-7.
148 # Now fold the 112 bytes in xmm0-xmm6 into the 16 bytes in xmm7.
168 add $128-16, len
201 movdqu -16(buf, len), %xmm1
204 # xmm2 = high order part of second chunk: xmm7 left-shifted by 'len' bytes.
210 # xmm7 = first chunk: xmm7 right-shifted by '16-len' bytes.
[all …]
/linux-5.10/sound/pci/emu10k1/
Dp16v.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
9 * Rates: 44.1, 48, 96, 192.
17 * Corrected speaker output, so Front -> Front etc.
36 * Merging with snd-emu10k1 driver.
38 * One stereo channel at 24bit now works.
45 * Some stability problems when unloading the snd-p16v kernel module.
46 * --
53 * --
56 * P16V Chip: CA0151-DBS
[all …]
/linux-5.10/arch/powerpc/kernel/vdso64/
Dsigtramp.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
33 .quad 0,-21*8
39 .uleb128 9f - 1f; /* length */ \
52 .uleb128 9f - 1f; /* length */ \
61 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
68 .uleb128 9f - 1f; /* length */ \
94 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
99 .uleb128 9f - 1f; /* length */ \
102 .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
105 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
[all …]
/linux-5.10/include/sound/
Demu10k1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/pcm-indirect.h>
25 /* ------------------- DEFINES -------------------- */
29 #define MAXPAGES0 4096 /* 32 bit mode */
30 #define MAXPAGES1 8192 /* 31 bit mode */
37 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
38 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
39 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
55 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
57 /* accessed. For non per-channel registers the */
[all …]
/linux-5.10/arch/arm/crypto/
Dcrct10dif-ce-core.S2 // Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
75 .arch armv8-a
76 .fpu crypto-neon-fp-armv8
118 vld1.64 {q11-q12}, [buf]!
166 // the bit order match the polynomial coefficient order.
167 vld1.64 {q0-q1}, [buf]!
168 vld1.64 {q2-q3}, [buf]!
169 vld1.64 {q4-q5}, [buf]!
[all …]
/linux-5.10/arch/mips/loongson64/
Ddma.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/dma-direct.h>
9 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in phys_to_dma()
10 * Loongson-3's 48bit address space and embed it into 40bit */ in phys_to_dma()
18 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in dma_to_phys()
19 * Loongson-3's 48bit address space and embed it into 40bit */ in dma_to_phys()
/linux-5.10/arch/alpha/kernel/
Dsys_wildfire.c1 // SPDX-License-Identifier: GPL-2.0
41 int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1); in wildfire_update_irq_hw()
42 int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1); in wildfire_update_irq_hw()
49 " got irq %d for non-existent PCA %d" in wildfire_update_irq_hw()
57 enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */ in wildfire_update_irq_hw()
72 enable0 = (unsigned long *) &pca->pca_int[0].enable; in wildfire_init_irq_hw()
73 enable1 = (unsigned long *) &pca->pca_int[1].enable; in wildfire_init_irq_hw()
74 enable2 = (unsigned long *) &pca->pca_int[2].enable; in wildfire_init_irq_hw()
75 enable3 = (unsigned long *) &pca->pca_int[3].enable; in wildfire_init_irq_hw()
77 target0 = (unsigned long *) &pca->pca_int[0].target; in wildfire_init_irq_hw()
[all …]
/linux-5.10/drivers/gpu/drm/amd/amdkfd/
Dkfd_flat_memory.c43 * Access to ATC/IOMMU mapped memory w/ associated extension of VA to 48b
56 * System Unified Address - SUA
80 * HSA64 - ATC/IOMMU 64b
85 * so the actual VA carried to translation is 48b. There is a “hole” in
105 * to a 49b address. This 49b address is constituted of an “ATC” bit
106 * plus a 48b virtual address. This 49b address is what is passed to the
107 * translation hardware. ATC==0 means the 48b address is a GPUVM address
109 * ATC==1 means the 48b address is intended to be translated via IOMMU
114 * aperture, we subtract the GPUVM_Base address and set the ATC bit to zero
126 * is defined as a 48b address w/ an ATC bit. For this usage a given
[all …]
/linux-5.10/arch/alpha/oprofile/
Dop_model_ev5.c19 The 21164 (EV5) and 21164PC (PCA65) vary in the bit placement and
21 at this point, arrange for the difference in bit placement to be
36 PCSEL1: 24-39 in common_reg_setup()
37 CBOX1: 40-47 in common_reg_setup()
38 PCSEL2: 48-63 in common_reg_setup()
39 CBOX2: 64-71 in common_reg_setup()
54 event = 12+48; in common_reg_setup()
59 /* Convert the event numbers onto mux_select bit mask. */ in common_reg_setup()
65 ctl |= (event - 24) << 4; in common_reg_setup()
66 else if (event < 48) in common_reg_setup()
[all …]
/linux-5.10/include/soc/fsl/
Dbman.h1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
34 /* wrapper for 48-bit buffers */
38 __be16 bpid; /* hi 8-bits reserved */
39 __be16 hi; /* High 16-bits of 48-bit address */
40 __be32 lo; /* Low 32-bits of 48-bit address */
46 * Restore the 48 bit address previously stored in BMan
51 return be64_to_cpu(buf->data) & 0xffffffffffffLLU; in bm_buf_addr()
56 return be64_to_cpu(buf->data) & 0xffffffffffffLLU; in bm_buffer_get64()
61 buf->hi = cpu_to_be16(upper_32_bits(addr)); in bm_buffer_set64()
62 buf->lo = cpu_to_be32(lower_32_bits(addr)); in bm_buffer_set64()
[all …]
/linux-5.10/drivers/net/ethernet/apm/xgene/
Dxgene_enet_hw.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Applied Micro X-Gene SoC Ethernet Driver
22 u32 end = start + len - 1; in xgene_set_bits()
41 #define OVERWRITE BIT(31)
42 #define IS_BUFFER_POOL BIT(20)
43 #define PREFETCH_BUF_EN BIT(21)
61 #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))
62 #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos))
92 #define ACCEPTLERR BIT(19)
93 #define QCOHERENT BIT(4)
[all …]
/linux-5.10/drivers/crypto/marvell/octeontx/
Dotx_cpt_hw_types.h1 /* SPDX-License-Identifier: GPL-2.0
46 #define OTX_CPT_VF_INTR_MBOX_MASK BIT(0)
47 #define OTX_CPT_VF_INTR_DOVF_MASK BIT(1)
48 #define OTX_CPT_VF_INTR_IRDE_MASK BIT(2)
49 #define OTX_CPT_VF_INTR_NWRP_MASK BIT(3)
50 #define OTX_CPT_VF_INTR_SERR_MASK BIT(4)
154 * CPT OcteonTX VF MSI-X Vector Enumeration
155 * Enumerates the MSI-X interrupt vectors.
167 * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
179 * Address must be 16-byte aligned.
[all …]
/linux-5.10/drivers/clk/pxa/
Dclk-pxa3xx.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c
9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
14 #include <linux/clk-provider.h>
18 #include <mach/pxa3xx-regs.h>
20 #include <dt-bindings/clock/pxa-clock.h>
21 #include "clk-pxa.h"
106 return (parent_rate / 48) * smcfs_mult[(acsr >> 23) & 0x7] / in clk_pxa3xx_smemc_get_rate()
126 #define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENB : &CKENA) argument
128 div_hp, bit, is_lp, flags) \ argument
[all …]
/linux-5.10/arch/powerpc/lib/
Dchecksum_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains assembly-language implementations
4 * of IP-style 1's complement checksum routines.
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
19 * and adds in "sum" (32-bit).
35 rldicl. r6,r3,64-1,64-2 /* r6 = (r3 >> 1) & 0x3 */
62 stdu r1,-STACKFRAMESIZE(r1)
86 ld r15,48(r3)
113 ld r15,48(r3)
176 rldicl r4,r0,32,0 /* fold two 32 bit halves together */
[all …]

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