19    The 21164 (EV5) and 21164PC (PCA65) vary in the bit placement and
21    at this point, arrange for the difference in bit placement to be
36 		PCSEL1:	24-39  in common_reg_setup()
37 		 CBOX1: 40-47  in common_reg_setup()
38 		PCSEL2: 48-63  in common_reg_setup()
39 		 CBOX2: 64-71  in common_reg_setup()
54 				event = 12+48;  in common_reg_setup()
59 		/* Convert the event numbers onto mux_select bit mask.  */  in common_reg_setup()
65 			ctl |= (event - 24) << 4;  in common_reg_setup()
66 		else if (event < 48)  in common_reg_setup()
67 			ctl |= (event - 40) << cbox1_ofs | 15 << 4;  in common_reg_setup()
69 			ctl |= event - 48;  in common_reg_setup()
71 			ctl |= (event - 64) << cbox2_ofs | 15;  in common_reg_setup()
73 	reg->mux_select = ctl;  in common_reg_setup()
79 	ctl |= !sys->enable_pal << 9;  in common_reg_setup()
80 	ctl |= !sys->enable_kernel << 8;  in common_reg_setup()
81 	ctl |= !sys->enable_user << 30;  in common_reg_setup()
82 	reg->proc_mode = ctl;  in common_reg_setup()
105 		ctl |= hilo << (8 - i*2);  in common_reg_setup()
106 		reset |= (max - count) << (48 - 16*i);  in common_reg_setup()
110 	reg->freq = ctl;  in common_reg_setup()
111 	reg->reset_values = reset;  in common_reg_setup()
112 	reg->need_reset = need_reset;  in common_reg_setup()
138 	wrperfmon(2, reg->mux_select);  in ev5_cpu_setup()
139 	wrperfmon(3, reg->proc_mode);  in ev5_cpu_setup()
140 	wrperfmon(4, reg->freq);  in ev5_cpu_setup()
141 	wrperfmon(6, reg->reset_values);  in ev5_cpu_setup()
146    for CTR to the value stored in REG->RESET_VALUES.
161 	mask = (ctr == 0 ? 0xfffful << 48  in ev5_reset_ctr()
167 	reset_values = reg->reset_values;  in ev5_reset_ctr()
169 	if ((reg->proc_mode & not_pk) == not_pk) {  in ev5_reset_ctr()
171 		values = (reset_values & mask) | (values & ~mask & -2);  in ev5_reset_ctr()
174 		wrperfmon(0, -1);  in ev5_reset_ctr()
176 		values = (reset_values & mask) | (values & ~mask & -2);  in ev5_reset_ctr()
178 		wrperfmon(1, reg->enable);  in ev5_reset_ctr()