Searched +full:3 +full:base +full:- +full:x (Results 1 – 25 of 351) sorted by relevance
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2 Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=671088644 64 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)6 === Check allocation status regression with -B ===8 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864 backing_file=TEST_DIR/t.IMGFMT.base backin…10 3 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)13 0x300000 0x3d00000 TEST_DIR/t.IMGFMT.base17 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864 backing_file=TEST_DIR/t.IMGFMT.base backin…19 3 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)21 3 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)23 3 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)[all …]
2 == create base ==3 Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=167772165 == writing whole image base ==7 16 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)9 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=16777216 backing_file=TEST_DIR/t.IMGFMT.base backin…13 16 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)15 == verify pattern base ==17 16 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)21 16 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)23 == committing layer into base ==[all …]
5 Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=671088646 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864 backing_file=TEST_DIR/t.IMGFMT.base backin…8 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)9 qemu-img: Failed to empty blkdebug:TEST_DIR/blkdebug.conf:TEST_DIR/t.IMGFMT: Input/output error14 Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=6710886415 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864 backing_file=TEST_DIR/t.IMGFMT.base backin…17 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)18 qemu-img: Failed to empty blkdebug:TEST_DIR/blkdebug.conf:TEST_DIR/t.IMGFMT: Input/output error27 Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=6710886428 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864 backing_file=TEST_DIR/t.IMGFMT.base backin…[all …]
6 Formatting 'TEST_DIR/t.IMGFMT.base', fmt=raw size=10485767 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1048576 backing_file=TEST_DIR/t.IMGFMT.base backing…8 write -q -P PATTERN 0 1k10 write -q -P PATTERN 3k 51212 write -q -P PATTERN 5k 1k14 write -q -P PATTERN 6k 2k16 write -q -P PATTERN 8k 6k18 write -q -P PATTERN 15k 4k20 write -q -P PATTERN 32k 1k22 write -q -P PATTERN 63k 4k[all …]
7 128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)9 version 352 128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)59 128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)61 128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)67 version 3110 128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)112 128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)120 128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)123 version 3[all …]
5 Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=22020101126 Formatting 'TEST_DIR/t.IMGFMT.itmd', fmt=IMGFMT size=2202010112 backing_file=TEST_DIR/t.IMGFMT.base…9 192 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)11 128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)13 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)15 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)18 192 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)20 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)22 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)24 64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)[all …]
3 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728 backing_file=TEST_DIR/t.IMGFMT.base backi…7 Testing: -drive file=TEST_DIR/t.qcow2,format=qcow2,unknown_opt=,if=none,id=drive08 QEMU_PROG: -drive file=TEST_DIR/t.qcow2,format=qcow2,unknown_opt=,if=none,id=drive0: Block format '…10 Testing: -drive file=TEST_DIR/t.qcow2,format=qcow2,unknown_opt=on,if=none,id=drive011 QEMU_PROG: -drive file=TEST_DIR/t.qcow2,format=qcow2,unknown_opt=on,if=none,id=drive0: Block format…13 Testing: -drive file=TEST_DIR/t.qcow2,format=qcow2,unknown_opt=1234,if=none,id=drive014 QEMU_PROG: -drive file=TEST_DIR/t.qcow2,format=qcow2,unknown_opt=1234,if=none,id=drive0: Block form…16 Testing: -drive file=TEST_DIR/t.qcow2,format=qcow2,unknown_opt=foo,if=none,id=drive017 QEMU_PROG: -drive file=TEST_DIR/t.qcow2,format=qcow2,unknown_opt=foo,if=none,id=drive0: Block forma…22 Testing: -drive file=TEST_DIR/t.qcow2,format=qcow2,file.unknown_opt=[all …]
4 * Copyright (c) 2003-2004 Vassili Karpov (malc)27 #include "hw/qdev-properties.h"31 #include "qemu/main-loop.h"68 static const int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};76 if (-1 == ichan) { in i8257_write_page()77 dolog ("invalid channel %#x %#x\n", nport, data); in i8257_write_page()80 d->regs[ichan].page = data; in i8257_write_page()89 if (-1 == ichan) { in i8257_write_pageh()90 dolog ("invalid channel %#x %#x\n", nport, data); in i8257_write_pageh()93 d->regs[ichan].pageh = data; in i8257_write_pageh()[all …]
4 * Copyright (c) 2014-2020, IBM Corporation.7 * COPYING file in the top-level directory.13 #include "hw/pci-host/pnv_phb3_regs.h"14 #include "hw/pci-host/pnv_phb.h"15 #include "hw/pci-host/pnv_phb3.h"21 #include "hw/qdev-properties.h"27 (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__)31 PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); in pnv_phb3_find_cfg_dev()32 uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3]; in pnv_phb3_find_cfg_dev()41 return pci_find_device(pci->bus, bus, devfn); in pnv_phb3_find_cfg_dev()[all …]
2 #include "hw/acpi/aml-build.h"3 #include "hw/pci-host/gpex.h"24 aml_append(pkg, aml_name("L%.02X%X", bus_num, gsi)); in acpi_dsdt_add_pci_route_table()34 Aml *dev_gsi = aml_device("L%.02X%X", bus_num, i); in acpi_dsdt_add_pci_route_table()62 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); in acpi_dsdt_add_pci_osc()66 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is in acpi_dsdt_add_pci_osc()68 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 in acpi_dsdt_add_pci_osc()70 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); in acpi_dsdt_add_pci_osc()73 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); in acpi_dsdt_add_pci_osc()75 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); in acpi_dsdt_add_pci_osc()[all …]
4 * Copyright (c) 2018-2020, IBM Corporation.7 * COPYING file in the top-level directory.14 #include "hw/pci-host/pnv_phb4_regs.h"15 #include "hw/pci-host/pnv_phb4.h"21 #include "hw/qdev-properties.h"27 (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__)31 (pec)->chip_id, (pec)->index, ## __VA_ARGS__)35 PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); in pnv_phb4_find_cfg_dev()36 uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3]; in pnv_phb4_find_cfg_dev()49 return pci_find_device(pci->bus, bus, devfn); in pnv_phb4_find_cfg_dev()[all …]
... = 0x%02lx) L1: D-cache 32 KiB enabled I-cache 32 KiB enabled ...
4 * Copyright (c) 2005-2007 CodeSourcery23 #include "exec/translation-block.h"25 #include "tcg/tcg-op.h"27 #include "qemu/qemu-print.h"29 #include "exec/helper-proto.h"30 #include "exec/helper-gen.h"36 #include "exec/helper-info.c.inc"50 static char cpu_reg_names[2 * 8 * 3 + 5 * 4];82 -offsetof(M68kCPU, env) + in m68k_tcg_init()85 -offsetof(M68kCPU, env) + in m68k_tcg_init()[all …]
25 /* We only support generating code for 64-bit mode. */134 tcg_debug_assert(slot >= 0 && slot <= 3);138 #define INSN_OP(x) ((x) << 30)139 #define INSN_OP2(x) ((x) << 22)140 #define INSN_OP3(x) ((x) << 19)141 #define INSN_OPF(x) ((x) << 5)142 #define INSN_RD(x) ((x) << 25)143 #define INSN_RS1(x) ((x) << 14)144 #define INSN_RS2(x) (x)145 #define INSN_ASI(x) ((x) << 5)[all …]
4 Copyright(c) 1999 - 2006 Intel Corporation.23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-649737 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */38 #define E1000_EIAC 0x000DC /* Ext. Interrupt Auto Clear - RW */39 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */40 #define E1000_EITR 0x000E8 /* Extended Interrupt Throttling Rate - RW */41 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */42 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */43 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */[all …]
22 #include "qemu/qemu-print.h"101 if (env->hflags & HF_CS64_MASK) { in cpu_x86_dump_seg_cache()102 qemu_fprintf(f, "%-3s=%04x %016" PRIx64 " %08x %08x", name, in cpu_x86_dump_seg_cache()103 sc->selector, sc->base, sc->limit, in cpu_x86_dump_seg_cache()104 sc->flags & 0x00ffff00); in cpu_x86_dump_seg_cache()108 qemu_fprintf(f, "%-3s=%04x %08x %08x %08x", name, sc->selector, in cpu_x86_dump_seg_cache()109 (uint32_t)sc->base, sc->limit, in cpu_x86_dump_seg_cache()110 sc->flags & 0x00ffff00); in cpu_x86_dump_seg_cache()113 if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK)) in cpu_x86_dump_seg_cache()117 (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT); in cpu_x86_dump_seg_cache()[all …]
4 # Test qemu-img bitmap handling6 # Copyright (C) 2018-2021 Red Hat, Inc.33 trap "_cleanup; exit \$status" 0 1 2 3 1548 # Filter irrelevant format-specific information from the qemu-img info52 grep -v -e 'compat' -e 'compression type' -e 'data file' -e 'extended l2' \53 -e 'lazy refcounts' -e 'refcount bits'61 TEST_IMG="$TEST_IMG.base" _make_test_img 10M62 $QEMU_IMG bitmap --add -f $IMGFMT "$TEST_IMG.base" b063 $QEMU_IO -c 'w 3M 1M' -f $IMGFMT "$TEST_IMG.base" | _filter_qemu_io68 _make_test_img -b "$ORIG_IMG.base" -F $IMGFMT 10M[all …]
24 #include "exec/helper-proto.h"25 #include "accel/tcg/cpu-ldst.h"28 #include "helper-tcg.h"31 #include "tcg-cpu.h"37 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \40 env->regs[R_ESP] = (uint32_t)(val); \42 env->regs[R_ESP] = (val); \48 env->regs[R_ESP] = (env->regs[R_ESP] & ~(sp_mask)) | \66 sa->sp -= 2; in pushw()67 cpu_stw_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask), in pushw()[all …]
23 #include "signal-common.h"32 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; in target_cpu_init()33 env->hflags |= HF_PE_MASK | HF_CPL_MASK; in target_cpu_init()34 if (env->features[FEAT_1_EDX] & CPUID_SSE) { in target_cpu_init()35 env->cr[4] |= CR4_OSFXSR_MASK; in target_cpu_init()36 env->hflags |= HF_OSFXSR_MASK; in target_cpu_init()40 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { in target_cpu_init()44 env->cr[4] |= CR4_PAE_MASK; in target_cpu_init()45 env->efer |= MSR_EFER_LMA | MSR_EFER_LME; in target_cpu_init()46 env->hflags |= HF_LMA_MASK; in target_cpu_init()[all …]
23 #include "signal-common.h"32 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; in target_cpu_init()33 env->hflags |= HF_PE_MASK | HF_CPL_MASK; in target_cpu_init()34 if (env->features[FEAT_1_EDX] & CPUID_SSE) { in target_cpu_init()35 env->cr[4] |= CR4_OSFXSR_MASK; in target_cpu_init()36 env->hflags |= HF_OSFXSR_MASK; in target_cpu_init()40 env->eflags |= IF_MASK; in target_cpu_init()43 env->regs[R_EAX] = regs->eax; in target_cpu_init()44 env->regs[R_EBX] = regs->ebx; in target_cpu_init()45 env->regs[R_ECX] = regs->ecx; in target_cpu_init()[all …]
47 #define SYM_RESOLVE(base, r, s) ((s = pdb_resolve(base, r, #s)),\ argument48 s ? printf(#s" = 0x%016"PRIx64"\n", s) :\101 printf("[KiWaitNever] = 0x%016"PRIx64"\n", kwn); in get_kdbg()102 printf("[KiWaitAlways] = 0x%016"PRIx64"\n", kwa); in get_kdbg()147 .SegCs = s->cs.selector, in win_context_init_from_qemu_cpu_state()148 .SegSs = s->ss.selector, in win_context_init_from_qemu_cpu_state()149 .SegDs = s->ds.selector, in win_context_init_from_qemu_cpu_state()150 .SegEs = s->es.selector, in win_context_init_from_qemu_cpu_state()151 .SegFs = s->fs.selector, in win_context_init_from_qemu_cpu_state()152 .SegGs = s->gs.selector, in win_context_init_from_qemu_cpu_state()[all …]
1 /* SPDX-License-Identifier: MIT */3 * xen-x86_64.h5 * Guest OS interface to x86 64-bit Xen.7 * Copyright (c) 2004-2006, K A Fraser15 * Input: %rdi, %rsi, %rdx, %r10, %r8, %r9 (arguments 1-6)18 * call hypercall_page + hypercall-number * 3219 * Clobbered: argument registers (e.g., 2-arg hypercall clobbers %rdi,%rsi)23 * 64-bit segment selectors24 * These flat segments are in the Xen-private section of every GDT. Since these68 #define MACH2PHYS_NR_ENTRIES ((MACH2PHYS_VIRT_END-MACH2PHYS_VIRT_START)>>3)[all …]
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.38 #include "hw/qdev-properties.h"84 uint32_t req_quad_base_n; /* Base of registers quad. Multiply it by 4 and in exynos4210_combiner_read()86 uint32_t grp_quad_base_n; /* Base of group quad */ in exynos4210_combiner_read()92 reg_n = (offset - (req_quad_base_n << 4)) >> 2; in exynos4210_combiner_read()96 return s->icipsr[reg_n]; in exynos4210_combiner_read()104 val |= s->group[grp_quad_base_n].src_pending; in exynos4210_combiner_read()105 val |= s->group[grp_quad_base_n + 1].src_pending << 8; in exynos4210_combiner_read()106 val |= s->group[grp_quad_base_n + 2].src_pending << 16; in exynos4210_combiner_read()107 val |= s->group[grp_quad_base_n + 3].src_pending << 24; in exynos4210_combiner_read()[all …]
94 /* The Win64 ABI has xmm6-xmm15 as caller-saves, and we do not save95 any of them. Therefore only allow xmm0-xmm5 to be allocated. */189 value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr);198 value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr);235 * TESTQ -> TESTL (uint32_t)236 * TESTQ -> BT (is_power_of_2)253 # define LOWREGMASK(x) ((x) & 7)279 #define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */281 #define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3))282 #define OPC_AND_GvEv (OPC_ARITH_GvEv | (ARITH_AND << 3))[all …]
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.23 #include "accel/tcg/cpu-ldst.h"24 #include "tcg/tcg-op.h"25 #include "exec/helper-proto.h"26 #include "exec/helper-gen.h"28 #include "exec/translation-block.h"30 #include "qemu/qemu-print.h"35 #include "exec/helper-info.c.inc"39 (((src) >> start) & ((1 << (end - start + 1)) - 1))63 DisasContextBase base; member[all …]